From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org
Subject: Re: [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Date: Thu, 19 Aug 2021 00:41:28 +0200 [thread overview]
Message-ID: <CAAeLtUD-5Rv6Sc8mR-f2PHHSVyasAEn4z8TK1-bwsirks3+Qng@mail.gmail.com> (raw)
In-Reply-To: <a03ce617-6bc6-0b23-e7d5-65ab03ea7e7e@linaro.org>
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I will provide a v3 to restore bisectability,
On Thu, 19 Aug 2021 at 00:39, Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 8/18/21 10:32 AM, Philipp Tomsich wrote:
> > +++ b/target/riscv/cpu.h
> > @@ -67,7 +67,6 @@
> > #define RVS RV('S')
> > #define RVU RV('U')
> > #define RVH RV('H')
> > -#define RVB RV('B')
>
> This patch does not compile by itself, because RVB is still used in
> insn_trans/trans_rvb.c.inc.
>
>
> r~
>
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next prev parent reply other threads:[~2021-08-18 22:42 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-18 20:32 [PATCH v2 0/3] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-08-18 20:32 ` [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-08-18 22:39 ` Richard Henderson
2021-08-18 22:41 ` Philipp Tomsich [this message]
2021-08-18 20:32 ` [PATCH v2 2/3] target/riscv: update Zb[abcs] to 1.0.0 (public review) specification Philipp Tomsich
2021-08-19 1:09 ` Richard Henderson
2021-08-18 20:32 ` [PATCH v2 3/3] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
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