From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 143AAC433FE for ; Tue, 24 May 2022 12:33:55 +0000 (UTC) Received: from localhost ([::1]:42230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ntTjW-0001gM-0T for qemu-devel@archiver.kernel.org; Tue, 24 May 2022 08:33:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ntTN2-0004tI-If for qemu-devel@nongnu.org; Tue, 24 May 2022 08:10:40 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:35796) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ntTN0-0006sx-GY for qemu-devel@nongnu.org; Tue, 24 May 2022 08:10:40 -0400 Received: by mail-wr1-x42f.google.com with SMTP id x12so1166120wrg.2 for ; Tue, 24 May 2022 05:10:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=AzXZ0UGwJCBngpgI4uD8Azmg5dEBbjNzTqsntyumh3E=; b=zt19TAKGS29nj9f1IqibbAoDCuibCuEnY2uxGsd2ylIfPoWljMTUbAgA2YGf8Tr8uL IJFNZZMRUCz+XTyzy3IAXWxEVoHRanRpm4dF35E/Esdjc5IWLWO3TAvU9kXTnmd9q512 NLS7dmY3vUVmkhu4vmF5vW6NEUXuhiCZUWBUjI0E/5qDZUstC8/uMg+1rgodkGBNOGWb ZyOdcs4CuCURiwsRK6nigXJSxiwIWXchCoeIFrMZslgv0BfeXkoAcQHDFlLLJjTDb+k5 z/ZPTXSpXCPe9jbqKmjkl6hJc30EvvTem32yKi+hbYguy5NDu2AU0DAFy8bqlW4+Em1b 5dJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=AzXZ0UGwJCBngpgI4uD8Azmg5dEBbjNzTqsntyumh3E=; b=Wl+AcT4i0mkd5fopLlHNYm5OX+VV1gBzc5fYyDX7gCGdZcW5waGOSwnv7g7YPQKHla AvGXz3UgeV2mI+8i69zt++bq9ZV17As2rjCQyY36hQgU+J3j+WXcayCAv40WqsgVgU4z +OzVc5vemjNQNRsW8iyqgAXLhsO0mz5RupVL0VimLLgcU17CglVLxBNYDIj5t4AdYyz3 azAMD397Gd2kB8DZrsFtx317gawHgMrw1619e4XhQq8JqNYJlIKtjV9y7/A0V39zBr2Q Rs0tIi5g+c3VwU2/C24ZCSOrWz0gJk0WdQFgV/XNGELqJu/mV8LRs6LxkrHHNAQCClet Vfjg== X-Gm-Message-State: AOAM532Rddzz9TUrmbfTzAlPvHguXpEwdbJhXaMacnz6zho3tfNbEDnI 1JzK4P4XyzktWJAjkqV26u6XBgIYcxBXfE77QTEjpQ== X-Google-Smtp-Source: ABdhPJzVz4OWO5u4A1821BG+t8orPZnkQ+O6wPQtwvwGJDa4mj890YntzLFurL2B76GM7sibH5xc98H6gPkSe9UXKDU= X-Received: by 2002:a05:6000:1f18:b0:20f:e61b:520e with SMTP id bv24-20020a0560001f1800b0020fe61b520emr6532049wrb.214.1653394236298; Tue, 24 May 2022 05:10:36 -0700 (PDT) MIME-Version: 1.0 References: <20220511144528.393530-1-apatel@ventanamicro.com> <20220511144528.393530-8-apatel@ventanamicro.com> In-Reply-To: From: Anup Patel Date: Tue, 24 May 2022 17:40:24 +0530 Message-ID: Subject: Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match To: Alistair Francis Cc: Anup Patel , Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Atish Patra , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Received-SPF: none client-ip=2a00:1450:4864:20::42f; envelope-from=anup@brainfault.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, May 24, 2022 at 3:22 AM Alistair Francis wrote: > > On Fri, May 20, 2022 at 1:07 AM Anup Patel wrote: > > > > On Tue, May 17, 2022 at 5:46 AM Alistair Francis wrote: > > > > > > On Thu, May 12, 2022 at 12:52 AM Anup Patel wrote: > > > > > > > > We should disable extensions in riscv_cpu_realize() if minimum required > > > > priv spec version is not satisfied. This also ensures that machines with > > > > priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter > > > > extensions. > > > > > > > > Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the > > > > device tree") > > > > Signed-off-by: Anup Patel > > > > > > This will potentially confuse users as we just disable the extension > > > without telling them. > > > > > > Could we not just leave this as is and let users specify the > > > extensions they want? Then it's up to them to specify the correct > > > combinations > > > > The ISA extensions are not independent of the Priv spec version. > > > > For example, we have bits for Sstc, Svpbmt, and Zicbo[m|p|z] extensions > > in xenvcfg CSRs which are only available for Priv v1.12 spec. > > > > We can't allow users to enable extensions which don't meet > > the Priv spec version requirements. > > Fair point. Ok we should at least report a warning if any of these are > set though Okay, I will update this patch accordingly. Regards, Anup > > Alistair > > > > > Regards, > > Anup > > > > > > > > Alistair > > > > > > > --- > > > > target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++ > > > > 1 file changed, 34 insertions(+) > > > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > > index f3b61dfd63..25a4ba3e22 100644 > > > > --- a/target/riscv/cpu.c > > > > +++ b/target/riscv/cpu.c > > > > @@ -541,6 +541,40 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > > > set_priv_version(env, priv_version); > > > > } > > > > > > > > + /* Force disable extensions if priv spec version does not match */ > > > > + if (env->priv_ver < PRIV_VERSION_1_12_0) { > > > > + cpu->cfg.ext_h = false; > > > > + cpu->cfg.ext_v = false; > > > > + cpu->cfg.ext_zfh = false; > > > > + cpu->cfg.ext_zfhmin = false; > > > > + cpu->cfg.ext_zfinx = false; > > > > + cpu->cfg.ext_zhinx = false; > > > > + cpu->cfg.ext_zhinxmin = false; > > > > + cpu->cfg.ext_zdinx = false; > > > > + cpu->cfg.ext_zba = false; > > > > + cpu->cfg.ext_zbb = false; > > > > + cpu->cfg.ext_zbc = false; > > > > + cpu->cfg.ext_zbkb = false; > > > > + cpu->cfg.ext_zbkc = false; > > > > + cpu->cfg.ext_zbkx = false; > > > > + cpu->cfg.ext_zbs = false; > > > > + cpu->cfg.ext_zk = false; > > > > + cpu->cfg.ext_zkn = false; > > > > + cpu->cfg.ext_zknd = false; > > > > + cpu->cfg.ext_zkne = false; > > > > + cpu->cfg.ext_zknh = false; > > > > + cpu->cfg.ext_zkr = false; > > > > + cpu->cfg.ext_zks = false; > > > > + cpu->cfg.ext_zksed = false; > > > > + cpu->cfg.ext_zksh = false; > > > > + cpu->cfg.ext_zkt = false; > > > > + cpu->cfg.ext_zve32f = false; > > > > + cpu->cfg.ext_zve64f = false; > > > > + cpu->cfg.ext_svinval = false; > > > > + cpu->cfg.ext_svnapot = false; > > > > + cpu->cfg.ext_svpbmt = false; > > > > + } > > > > + > > > > if (cpu->cfg.mmu) { > > > > riscv_set_feature(env, RISCV_FEATURE_MMU); > > > > } > > > > -- > > > > 2.34.1 > > > > > > > >