From: Anup Patel <anup@brainfault.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
dylan@rivosinc.com, Bin Meng <bmeng.cn@gmail.com>,
Frank Chang <frank.chang@sifive.com>,
Jim Shu <jim.shu@sifive.com>
Subject: Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
Date: Sat, 14 May 2022 10:12:27 +0530 [thread overview]
Message-ID: <CAAhSdy1pJXrxgsCgUFnVZenSXLpcf8CPSS7x39nv1-StZLgRKA@mail.gmail.com> (raw)
In-Reply-To: <20220513221458.1192933-1-atishp@rivosinc.com>
On Sat, May 14, 2022 at 3:45 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> timecmp update function should be invoked with hartid for which
> timecmp is being updated. The following patch passes the incorrect
> hartid to the update function.
>
> Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> hw/intc/riscv_aclint.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
> index 0412edc98257..e6bceceefdbc 100644
> --- a/hw/intc/riscv_aclint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -233,7 +233,8 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
> continue;
> }
> riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
> - i, env->timecmp);
> + mtimer->hartid_base + i,
> + env->timecmp);
> }
> return;
> }
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2022-05-14 4:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-13 22:14 [PATCH] hw/intc: Pass correct hartid while updating mtimecmp Atish Patra
2022-05-14 2:21 ` Frank Chang
2022-05-14 4:42 ` Anup Patel [this message]
2022-05-16 22:41 ` Alistair Francis
2022-05-16 23:10 ` Alistair Francis
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