From: Anup Patel <anup@brainfault.org>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: alistair23@gmail.com, Palmer Dabbelt <palmer@sifive.com>,
qemu-riscv@nongnu.org, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [Qemu-riscv] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware
Date: Wed, 19 Jun 2019 10:46:24 +0530 [thread overview]
Message-ID: <CAAhSdy289EV2S2pYZP-VQNoiVHcV_stdgFYEj5Y01FsuZ+9E4A@mail.gmail.com> (raw)
In-Reply-To: <3d7dd8bc94dbfddf0c01cfc7f3bebc937d1e6894.1560904640.git.alistair.francis@wdc.com>
On Wed, Jun 19, 2019 at 6:21 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> If the user hasn't specified a firmware to load (with -bios) or
> specified no bios (with -bios none) then load OpenSBI by default. This
> allows users to boot a RISC-V kernel with just -kernel.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/boot.c | 28 ++++++++++++++++++++++++++++
> hw/riscv/sifive_u.c | 4 +---
> hw/riscv/virt.c | 4 +---
> include/hw/riscv/boot.h | 1 +
> 4 files changed, 31 insertions(+), 6 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 7f68035a3f..5f021591ed 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -18,6 +18,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu-common.h"
> #include "qemu/units.h"
> #include "qemu/error-report.h"
> #include "exec/cpu-defs.h"
> @@ -32,6 +33,12 @@
> # define KERNEL_BOOT_ADDRESS 0x80200000
> #endif
>
> +#if defined(TARGET_RISCV32)
> +# define BIOS_FILENAME "opensbi-riscv32-fw_jump.elf"
> +#else
> +# define BIOS_FILENAME "opensbi-riscv64-fw_jump.elf"
> +#endif
Based on my comment on PATCH4, BIOS_FILENAME should
be derived from QEMU machine name and TARGET_RISCVx
Agree ??
Regards,
Anup
> +
> static uint64_t kernel_translate(void *opaque, uint64_t addr)
> {
> MachineState *machine = opaque;
> @@ -47,6 +54,27 @@ static uint64_t kernel_translate(void *opaque, uint64_t addr)
> }
> }
>
> +void riscv_find_and_load_firmware(MachineState *machine)
> +{
> + char *firmware_filename;
> +
> + if (!machine->firmware) {
> + /* The user didn't specify a firmware, default to OpenSBI */
> + firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BIOS_FILENAME);
> + } else {
> + firmware_filename = machine->firmware;
> + }
> +
> + if (strcmp(firmware_filename, "none")) {
> + /* If not "none" load the firmware */
> + riscv_load_firmware(firmware_filename);
> + }
> +
> + if (!machine->firmware) {
> + g_free(firmware_filename);
> + }
> +}
> +
> target_ulong riscv_load_firmware(const char *firmware_filename)
> {
> uint64_t firmware_entry, firmware_start, firmware_end;
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 03a6c64d04..77666d0f4d 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -266,9 +266,7 @@ static void riscv_sifive_u_init(MachineState *machine)
> /* create device tree */
> create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
>
> - if (machine->firmware) {
> - riscv_load_firmware(machine->firmware);
> - }
> + riscv_find_and_load_firmware(machine);
>
> if (machine->kernel_filename) {
> riscv_load_kernel(machine, machine->kernel_filename);
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index d3670b5a7c..2a7e850666 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -380,9 +380,7 @@ static void riscv_virt_board_init(MachineState *machine)
> memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
> mask_rom);
>
> - if (machine->firmware) {
> - riscv_load_firmware(machine->firmware);
> - }
> + riscv_find_and_load_firmware(machine);
>
> if (machine->kernel_filename) {
> uint64_t kernel_entry = riscv_load_kernel(machine,
> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> index 6f586939c7..df2e2480e6 100644
> --- a/include/hw/riscv/boot.h
> +++ b/include/hw/riscv/boot.h
> @@ -20,6 +20,7 @@
> #ifndef RISCV_BOOT_H
> #define RISCV_BOOT_H
>
> +void riscv_find_and_load_firmware(MachineState *machine);
> target_ulong riscv_load_firmware(const char *firmware_filename);
> target_ulong riscv_load_kernel(MachineState *machine,
> const char *kernel_filename);
> --
> 2.22.0
>
>
next prev parent reply other threads:[~2019-06-19 5:17 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-19 0:38 [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions Alistair Francis
2019-06-19 15:16 ` Bin Meng
2019-06-19 18:24 ` Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware Alistair Francis
2019-06-19 15:16 ` Bin Meng
2019-06-19 15:25 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-06-19 15:30 ` Bin Meng
2019-06-19 21:00 ` Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support Alistair Francis
2019-06-19 15:16 ` Bin Meng
2019-06-19 21:01 ` Alistair Francis
2019-06-19 22:06 ` Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 4/5] roms: Add OpenSBI version 0.3 Alistair Francis
2019-06-19 5:14 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
2019-06-19 15:18 ` Bin Meng
2019-06-19 18:27 ` Alistair Francis
2019-06-21 5:41 ` Bin Meng
2019-06-21 22:41 ` Alistair Francis
2019-06-19 0:38 ` [Qemu-devel] [RFC v1 5/5] hw/riscv: Load OpenSBI as the default firmware Alistair Francis
2019-06-19 5:16 ` Anup Patel [this message]
2019-06-19 14:26 ` [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default Bin Meng
2019-06-19 14:29 ` Alistair Francis
2019-06-19 14:42 ` Bin Meng
2019-06-19 18:23 ` Alistair Francis
2019-06-20 8:16 ` [Qemu-devel] [Qemu-riscv] " Andrea Bolognani
2019-06-20 17:59 ` Alistair Francis
2019-06-20 18:43 ` David Abdurachmanov
2019-06-21 12:35 ` Andrea Bolognani
2019-06-27 13:49 ` Andrea Bolognani
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