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Tue, 07 Dec 2021 02:08:58 -0800 (PST) MIME-Version: 1.0 References: <20211026064227.2014502-1-anup.patel@wdc.com> <20211026064227.2014502-9-anup.patel@wdc.com> In-Reply-To: From: Anup Patel Date: Tue, 7 Dec 2021 15:38:47 +0530 Message-ID: Subject: Re: [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback To: Alistair Francis Content-Type: text/plain; charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42c (failed) Received-SPF: none client-ip=2a00:1450:4864:20::42c; envelope-from=anup@brainfault.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:RISC-V" , Sagar Karandikar , Anup Patel , "qemu-devel@nongnu.org Developers" , Atish Patra , Alistair Francis , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Nov 4, 2021 at 10:23 AM Alistair Francis wrote: > > On Tue, Oct 26, 2021 at 6:00 PM Anup Patel wrote: > > > > The AIA device emulation (such as AIA IMSIC) should be able to set > > (or provide) AIA ireg read-modify-write callback for each privilege > > level of a RISC-V HART. > > > > Signed-off-by: Anup Patel > > --- > > target/riscv/cpu.h | 19 +++++++++++++++++++ > > target/riscv/cpu_helper.c | 14 ++++++++++++++ > > 2 files changed, 33 insertions(+) > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 7182fadd21..ef4298dc69 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -239,6 +239,18 @@ struct CPURISCVState { > > uint64_t (*rdtime_fn)(uint32_t); > > uint32_t rdtime_fn_arg; > > > > + /* machine specific AIA ireg read-modify-write callback */ > > +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein) \ > > + ((((__vgein) & 0x3f) << 24) | (((__virt) & 0x1) << 20) | \ > > + (((__priv) & 0x3) << 16) | (__isel & 0xffff)) > > +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) > > +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) > > +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 20) & 0x1) > > +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 24) & 0x3f) > > These should be added when they are used Actually, these define help us encode/decode AIA indirect register number passed as "reg" parameter to aia_ireg_rmw_fn() below. Regards, Anup > > Alistair > > > + int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, > > + target_ulong *val, target_ulong new_val, target_ulong write_mask); > > + void *aia_ireg_rmw_fn_arg[4]; > > + > > /* True if in debugger mode. */ > > bool debugger; > > #endif > > @@ -380,6 +392,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); > > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ > > void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), > > uint32_t arg); > > +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, > > + int (*rmw_fn)(void *arg, > > + target_ulong reg, > > + target_ulong *val, > > + target_ulong new_val, > > + target_ulong write_mask), > > + void *rmw_fn_arg); > > #endif > > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index 04df3792a8..d70def1da8 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -375,6 +375,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), > > env->rdtime_fn_arg = arg; > > } > > > > +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, > > + int (*rmw_fn)(void *arg, > > + target_ulong reg, > > + target_ulong *val, > > + target_ulong new_val, > > + target_ulong write_mask), > > + void *rmw_fn_arg) > > +{ > > + if (priv <= PRV_M) { > > + env->aia_ireg_rmw_fn[priv] = rmw_fn; > > + env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; > > + } > > +} > > + > > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) > > { > > if (newpriv > PRV_M) { > > -- > > 2.25.1 > > > >