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From: Karthik <karthikshanmugam@gmail.com>
To: QEMU Developers <qemu-devel@nongnu.org>
Subject: [Qemu-devel] ARM invalid co-processor register
Date: Wed, 25 May 2016 11:14:34 +0530	[thread overview]
Message-ID: <CAAmr2Y8sJuoE3AQepAQBdATxpOYk57gMFMEzZJxBDjgLwj6=UQ@mail.gmail.com> (raw)

Hi,

CPU: Cortex R5F

I have this instruction that invalidates the entire data cache

MCR p15, 0, r0, c15, c5, 0


http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460c/Chdhgibd.html

This instruction generates undefined exception, and further debugging
showed it is because the co-processor register was not implemented.

To get around, I have added the below entry in the cortexr5_cp_reginfo[]
(target-arm/cpu.c)

{
    {.name = "INVALLDC", .cp=15, .opc1 = 0, .crn = 5, .opc2 = 0.
     .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_OVERRIDE},
}

or

I have to add
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);

So, which option is recommended?

Best regards,
Karthik

             reply	other threads:[~2016-05-25  5:44 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-25  5:44 Karthik [this message]
2016-05-25 12:27 ` [Qemu-devel] ARM invalid co-processor register Peter Maydell
2016-05-25 12:33   ` Karthik
2016-05-25 12:35     ` Peter Maydell
2016-05-25 12:44       ` Karthik

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