From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:58646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJeHT-0004SV-GY for qemu-devel@nongnu.org; Fri, 28 Oct 2011 00:43:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RJeHR-00040Y-WC for qemu-devel@nongnu.org; Fri, 28 Oct 2011 00:42:59 -0400 Received: from mail-ww0-f53.google.com ([74.125.82.53]:57452) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJeHR-00040O-Ov for qemu-devel@nongnu.org; Fri, 28 Oct 2011 00:42:57 -0400 Received: by wwi36 with SMTP id 36so4754490wwi.10 for ; Thu, 27 Oct 2011 21:42:55 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <4EA2AACE.3040602@web.de> References: <1319278273-32437-1-git-send-email-khansa@kics.edu.pk> <1319278273-32437-6-git-send-email-khansa@kics.edu.pk> <4EA2AACE.3040602@web.de> Date: Fri, 28 Oct 2011 09:42:55 +0500 Message-ID: From: Khansa Butt Content-Type: multipart/alternative; boundary=00504502cd6dd0ec5204b0548557 Subject: Re: [Qemu-devel] [PATCH v3 5/6] target-mips: Adding support for Cavium specific instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-1?Q?Andreas_F=E4rber?= , qemu-devel@nongnu.org --00504502cd6dd0ec5204b0548557 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On Sat, Oct 22, 2011 at 4:36 PM, Andreas F=E4rber w= rote: > Am 22.10.2011 12:11, schrieb khansa@kics.edu.pk: > > From: Khansa Butt > > Commit message should mention here at least that new registers are > introduced and that load/save format is being changed. > > > Signed-off-by: Khansa Butt > > Signed-off-by: Ehsan Ul Haq > > Signed-off-by: Abdul Qadeer > > Signed-off-by: Abdul Waheed > > --- > > > diff --git a/target-mips/cpu.h b/target-mips/cpu.h > > index 79e2558..9180ee9 100644 > > --- a/target-mips/cpu.h > > +++ b/target-mips/cpu.h > > @@ -173,6 +173,13 @@ struct TCState { > > target_ulong CP0_TCSchedule; > > target_ulong CP0_TCScheFBack; > > int32_t CP0_Debug_tcstatus; > > + /* Multiplier registers for Octeon */ > > + target_ulong MPL0; > > + target_ulong MPL1; > > + target_ulong MPL2; > > + target_ulong P0; > > + target_ulong P1; > > + target_ulong P2; > > }; > > > > typedef struct CPUMIPSState CPUMIPSState; > > > diff --git a/target-mips/machine.c b/target-mips/machine.c > > index be72b36..a274ce2 100644 > > --- a/target-mips/machine.c > > +++ b/target-mips/machine.c > > @@ -25,6 +25,12 @@ static void save_tc(QEMUFile *f, TCState *tc) > > qemu_put_betls(f, &tc->CP0_TCSchedule); > > qemu_put_betls(f, &tc->CP0_TCScheFBack); > > qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); > > + qemu_put_betls(f, &tc->MPL0); > > + qemu_put_betls(f, &tc->MPL1); > > MPL2 is not being saved but loaded below. > > > + qemu_put_betls(f, &tc->P0); > > + qemu_put_betls(f, &tc->P1); > > + qemu_put_betls(f, &tc->P2); > > + > > } > > > > static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) > > @@ -173,6 +179,12 @@ static void load_tc(QEMUFile *f, TCState *tc) > > qemu_get_betls(f, &tc->CP0_TCSchedule); > > qemu_get_betls(f, &tc->CP0_TCScheFBack); > > qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); > > + qemu_get_betls(f, &tc->MPL0); > > + qemu_get_betls(f, &tc->MPL1); > > + qemu_get_betls(f, &tc->MPL2); > > + qemu_get_betls(f, &tc->P0); > > + qemu_get_betls(f, &tc->P1); > > + qemu_get_betls(f, &tc->P2); > > } > > > > static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) > > You're saving new fields, so you'll need to bump the version somewhere. > For loading, since you're adding at the end, you might be able to make > your additions conditional on the to-be-bumped version. > I 'm not able to understand " bump the version somewhere" kindly explain this. > > I'm wondering whether those register and serialization additions could > and should be limited to TARGET_MIPS64. > > you want me to limit these registers to TARGET_OCTEON --00504502cd6dd0ec5204b0548557 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable

On Sat, Oct 22, 2011 at 4:36 PM, Andreas= F=E4rber <a= ndreas.faerber@web.de> wrote:
Am 22.10.2011 12:11, schrieb khansa@k= ics.edu.pk:
> From: Khansa Butt <khansa@kic= s.edu.pk>

Commit message should mention here at least that new registers are
introduced and that load/save format is being changed.

> Signed-off-by: Khansa Butt <k= hansa@kics.edu.pk>
> Signed-off-by: Ehsan Ul Haq <ehsan.ulhaq@kics.edu.pk>
> Signed-off-by: Abdul Qadeer <= qadeer@kics.edu.pk>
> Signed-off-by: Abdul Waheed <awaheed@kics.edu.pk>
> ---

> diff --git a/target-mips/cpu.h b/target-mips/c= pu.h
> index 79e2558..9180ee9 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -173,6 +173,13 @@ struct TCState {
> =A0 =A0 =A0target_ulong CP0_TCSchedule;
> =A0 =A0 =A0target_ulong CP0_TCScheFBack;
> =A0 =A0 =A0int32_t CP0_Debug_tcstatus;
> + =A0 =A0/* Multiplier registers for Octeon */
> + =A0 =A0target_ulong MPL0;
> + =A0 =A0target_ulong MPL1;
> + =A0 =A0target_ulong MPL2;
> + =A0 =A0target_ulong P0;
> + =A0 =A0target_ulong P1;
> + =A0 =A0target_ulong P2;
> =A0};
>
> =A0typedef struct CPUMIPSState CPUMIPSState;

> diff --git a/target-mips/machine.c b/target-mi= ps/machine.c
> index be72b36..a274ce2 100644
> --- a/target-mips/machine.c
> +++ b/target-mips/machine.c
> @@ -25,6 +25,12 @@ static void save_tc(QEMUFile *f, TCState *tc)
> =A0 =A0 =A0qemu_put_betls(f, &tc->CP0_TCSchedule);
> =A0 =A0 =A0qemu_put_betls(f, &tc->CP0_TCScheFBack);
> =A0 =A0 =A0qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
> + =A0 =A0qemu_put_betls(f, &tc->MPL0);
> + =A0 =A0qemu_put_betls(f, &tc->MPL1);

MPL2 is not being saved but loaded below.

> + =A0 =A0qemu_put_betls(f, &tc->P0);
> + =A0 =A0qemu_put_betls(f, &tc->P1);
> + =A0 =A0qemu_put_betls(f, &tc->P2);
> +
> =A0}
>
> =A0static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
> @@ -173,6 +179,12 @@ static void load_tc(QEMUFile *f, TCState *tc)
> =A0 =A0 =A0qemu_get_betls(f, &tc->CP0_TCSchedule);
> =A0 =A0 =A0qemu_get_betls(f, &tc->CP0_TCScheFBack);
> =A0 =A0 =A0qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
> + =A0 =A0qemu_get_betls(f, &tc->MPL0);
> + =A0 =A0qemu_get_betls(f, &tc->MPL1);
> + =A0 =A0qemu_get_betls(f, &tc->MPL2);
> + =A0 =A0qemu_get_betls(f, &tc->P0);
> + =A0 =A0qemu_get_betls(f, &tc->P1);
> + =A0 =A0qemu_get_betls(f, &tc->P2);
> =A0}
>
> =A0static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)

You're saving new fields, so you'll need to bump the version = somewhere.
For loading, since you're adding at the end, you might be able to make<= br> your additions conditional on the to-be-bumped version.

I 'm not able to understand " bump the version so= mewhere" =A0kindly
explain this.
=A0

I'm wondering whether those register and serialization additions could<= br> and should be limited to TARGET_MIPS64.

you want me to limit t= hese registers to TARGET_OCTEON
=A0

--00504502cd6dd0ec5204b0548557--