From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S8wS7-0000kW-8n for qemu-devel@nongnu.org; Sat, 17 Mar 2012 12:26:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S8wS5-0003e3-4T for qemu-devel@nongnu.org; Sat, 17 Mar 2012 12:25:58 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:35257) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S8wS4-0003dv-S0 for qemu-devel@nongnu.org; Sat, 17 Mar 2012 12:25:57 -0400 Received: by iafj26 with SMTP id j26so7977295iaf.4 for ; Sat, 17 Mar 2012 09:25:55 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1331938254-13348-1-git-send-email-sw@weilnetz.de> References: <1331938254-13348-1-git-send-email-sw@weilnetz.de> From: Blue Swirl Date: Sat, 17 Mar 2012 16:25:35 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] w64: Fix data type of next_tb and tcg_qemu_tb_exec List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefan Weil Cc: qemu-devel@nongnu.org Thanks, applied. On Fri, Mar 16, 2012 at 22:50, Stefan Weil wrote: > next_tb is the numeric value of a tcg target (=3D QEMU host) address. > > Using tcg_target_ulong instead of unsigned long shows this and makes > the code portable for hosts with an unusual size of long (w64). > > The type cast '(long)(next_tb & ~3)' was not needed (casting > unsigned long to long does not change the bits, and nor does > casting long to pointer for most (=3D all non w64) hosts. > It is removed here. > > Macro or function tcg_qemu_tb_exec is used to set next_tb. > The function also returns next_tb. Therefore tcg_qemu_tb_exec > must return a tcg_target_ulong. > > Signed-off-by: Stefan Weil > --- > =C2=A0cpu-exec.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A06 +++-= -- > =C2=A0tcg/tcg.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A02= +- > =C2=A0tcg/tci/tcg-target.h | =C2=A0 =C2=A02 +- > =C2=A0tci.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2= =A0 =C2=A04 ++-- > =C2=A04 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/cpu-exec.c b/cpu-exec.c > index bd5791f..0fa8325 100644 > --- a/cpu-exec.c > +++ b/cpu-exec.c > @@ -55,7 +55,7 @@ void cpu_resume_from_signal(CPUArchState *env, void *pu= c) > =C2=A0static void cpu_exec_nocache(CPUArchState *env, int max_cycles, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TranslationBlock *orig_tb) > =C2=A0{ > - =C2=A0 =C2=A0unsigned long next_tb; > + =C2=A0 =C2=A0tcg_target_ulong next_tb; > =C2=A0 =C2=A0 TranslationBlock *tb; > > =C2=A0 =C2=A0 /* Should never happen. > @@ -186,7 +186,7 @@ int cpu_exec(CPUArchState *env) > =C2=A0 =C2=A0 int ret, interrupt_request; > =C2=A0 =C2=A0 TranslationBlock *tb; > =C2=A0 =C2=A0 uint8_t *tc_ptr; > - =C2=A0 =C2=A0unsigned long next_tb; > + =C2=A0 =C2=A0tcg_target_ulong next_tb; > > =C2=A0 =C2=A0 if (env->halted) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!cpu_has_work(env)) { > @@ -565,7 +565,7 @@ int cpu_exec(CPUArchState *env) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if = ((next_tb & 3) =3D=3D 2) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 /* Instruction counter expired. =C2=A0*/ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 int insns_left; > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0tb =3D (TranslationBlock *)(long)(next_tb & ~3); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0tb =3D (TranslationBlock *)(next_tb & ~3); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 /* Restore PC. =C2=A0*/ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 cpu_pc_from_tb(env, tb); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 insns_left =3D env->icount_decr.u32; > diff --git a/tcg/tcg.h b/tcg/tcg.h > index cc223ea..1d23d40 100644 > --- a/tcg/tcg.h > +++ b/tcg/tcg.h > @@ -589,5 +589,5 @@ extern uint8_t code_gen_prologue[]; > =C2=A0/* TCG targets may use a different definition of tcg_qemu_tb_exec. = */ > =C2=A0#if !defined(tcg_qemu_tb_exec) > =C2=A0# define tcg_qemu_tb_exec(env, tb_ptr) \ > - =C2=A0 =C2=A0((long REGPARM (*)(void *, void *))code_gen_prologue)(env,= tb_ptr) > + =C2=A0 =C2=A0((tcg_target_ulong REGPARM (*)(void *, void *))code_gen_pr= ologue)(env, tb_ptr) > =C2=A0#endif > diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h > index b61e99a..30a0f21 100644 > --- a/tcg/tci/tcg-target.h > +++ b/tcg/tci/tcg-target.h > @@ -154,7 +154,7 @@ typedef enum { > > =C2=A0void tci_disas(uint8_t opc); > > -unsigned long tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); > +tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); > =C2=A0#define tcg_qemu_tb_exec tcg_qemu_tb_exec > > =C2=A0static inline void flush_icache_range(tcg_target_ulong start, > diff --git a/tci.c b/tci.c > index fb9ebef..70e7bfb 100644 > --- a/tci.c > +++ b/tci.c > @@ -429,9 +429,9 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, T= CGCond condition) > =C2=A0} > > =C2=A0/* Interpret pseudo code in tb. */ > -unsigned long tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr) > +tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_pt= r) > =C2=A0{ > - =C2=A0 =C2=A0unsigned long next_tb =3D 0; > + =C2=A0 =C2=A0tcg_target_ulong next_tb =3D 0; > > =C2=A0 =C2=A0 env =3D cpustate; > =C2=A0 =C2=A0 tci_reg[TCG_AREG0] =3D (tcg_target_ulong)env; > -- > 1.7.9 > >