From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:54422) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SP9FP-0006Zu-Jq for qemu-devel@nongnu.org; Tue, 01 May 2012 05:19:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SP9FN-0003T4-CA for qemu-devel@nongnu.org; Tue, 01 May 2012 05:19:51 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:49705) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SP9FN-0003SZ-5D for qemu-devel@nongnu.org; Tue, 01 May 2012 05:19:49 -0400 Received: by iafj26 with SMTP id j26so6631514iaf.4 for ; Tue, 01 May 2012 02:19:47 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Blue Swirl Date: Tue, 1 May 2012 09:19:27 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] Poking a sun4v machine List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Artyom Tarasenko Cc: qemu-devel On Mon, Apr 30, 2012 at 16:39, Artyom Tarasenko wrote= : > Tried to boot QEMU Niagara machine with the firmware from the > OpenSPARC T1 emulator ( www.opensparc.net/opensparc-t1/download.html ) > , and it dies very early. > The reason: in translate.c > > #define hypervisor(dc) (dc->mem_idx =3D=3D MMU_HYPV_IDX) > #define supervisor(dc) (dc->mem_idx >=3D MMU_KERNEL_IDX) > > and the dc->mem_idx is initialized like this: > > =C2=A0 =C2=A0if (env1->tl > 0) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0return MMU_NUCLEUS_IDX; > =C2=A0 =C2=A0} else if (cpu_hypervisor_mode(env1)) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0return MMU_HYPV_IDX; > =C2=A0 =C2=A0} else if (cpu_supervisor_mode(env1)) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0return MMU_KERNEL_IDX; > =C2=A0 =C2=A0} else { > =C2=A0 =C2=A0 =C2=A0 =C2=A0return MMU_USER_IDX; > =C2=A0 =C2=A0} > > Which seems to be conceptually incorrect. After reset tl =3D=3D MAXTL, bu= t > still super- and hyper-visor bits are set, so both supervisor(dc) and > hypervisor(dc) must return 1 which is impossible in the current > implementation. I don't think this is needed. The MMU index tells which TLB is used for guest virtual to host address translations, during tl =3D=3D MAXTL we want to use hypervisor mode translations. > > What would be the proper way to fix it? Make mem_idx bitmap, add two > more variables to DisasContext, or ...? > > Some other findings/questions: > > =C2=A0 =C2=A0/* Sun4v generic Niagara machine */ > =C2=A0 =C2=A0{ > =C2=A0 =C2=A0 =C2=A0 =C2=A0.default_cpu_model =3D "Sun UltraSparc T1", > =C2=A0 =C2=A0 =C2=A0 =C2=A0.console_serial_base =3D 0xfff0c2c000ULL, > > Where is this address coming from? The OpenSPARC Niagara machine has a > "dumb serial" at 0x1f10000000ULL. I think I actually used Ontario machine definitions. > > And the biggest issue: UA2005 (as well as UA2007) describe a totally > different format for a MMU TTE entry than the one sun4u CPU are using. > I think the best way to handle it would be splitting off Niagara > machine, and #defining MMU bits differently for sun4u and sun4v > machines. > > Do we the cases in qemu where more than two (qemu-system-xxx and > qemu-system-xxx64) binaries are produced? > Would the name qemu-system-sun4v fit the naming convention? > > Artyom > > -- > Regards, > Artyom Tarasenko > > solaris/sparc under qemu blog: http://tyom.blogspot.com/search/label/qemu