From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59837) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDKLy-0000fj-Hv for qemu-devel@nongnu.org; Thu, 29 Mar 2012 14:45:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDKLv-0000LT-Fd for qemu-devel@nongnu.org; Thu, 29 Mar 2012 14:45:46 -0400 Received: from mail-gx0-f173.google.com ([209.85.161.173]:64976) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDKLv-0000L3-7Z for qemu-devel@nongnu.org; Thu, 29 Mar 2012 14:45:43 -0400 Received: by ggnp2 with SMTP id p2so2160167ggn.4 for ; Thu, 29 Mar 2012 11:45:40 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1332894743-27418-4-git-send-email-rth@twiddle.net> References: <1332894743-27418-1-git-send-email-rth@twiddle.net> <1332894743-27418-4-git-send-email-rth@twiddle.net> From: Blue Swirl Date: Thu, 29 Mar 2012 18:45:19 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 03/14] tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On Wed, Mar 28, 2012 at 00:32, Richard Henderson wrote: > Current code doesn't actually work in 32-bit mode at all. =C2=A0Since > no one really noticed, drop the complication of v7 and v8 cpus. > Eliminate the --sparc_cpu configure option and standardize macro > testing on TCG_TARGET_REG_BITS / HOST_LONG_BITS > > Signed-off-by: Richard Henderson > --- > =C2=A0configure =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 = 41 ++++------------------------------------- > =C2=A0disas.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| = =C2=A0 =C2=A06 ------ > =C2=A0dyngen-exec.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A04 +-= -- > =C2=A0exec.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | = =C2=A0 12 +++++------- > =C2=A0qemu-timer.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A08 ++= +++--- > =C2=A0tcg/sparc/tcg-target.c | =C2=A0 20 +++++--------------- > =C2=A0tcg/sparc/tcg-target.h | =C2=A0 =C2=A07 ++++--- > =C2=A0tcg/tcg.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 = =C2=A03 ++- > =C2=A08 files changed, 26 insertions(+), 75 deletions(-) > > diff --git a/configure b/configure > index 80ca430..7741ba9 100755 > --- a/configure > +++ b/configure > @@ -86,7 +86,6 @@ source_path=3D`dirname "$0"` > =C2=A0cpu=3D"" > =C2=A0interp_prefix=3D"/usr/gnemul/qemu-%M" > =C2=A0static=3D"no" > -sparc_cpu=3D"" > =C2=A0cross_prefix=3D"" > =C2=A0audio_drv_list=3D"" > =C2=A0audio_card_list=3D"ac97 es1370 sb16 hda" > @@ -216,21 +215,6 @@ for opt do > =C2=A0 ;; > =C2=A0 --disable-debug-info) debug_info=3D"no" > =C2=A0 ;; > - =C2=A0--sparc_cpu=3D*) > - =C2=A0 =C2=A0sparc_cpu=3D"$optarg" > - =C2=A0 =C2=A0case $sparc_cpu in > - =C2=A0 =C2=A0v7|v8|v8plus|v8plusa) > - =C2=A0 =C2=A0 =C2=A0cpu=3D"sparc" > - =C2=A0 =C2=A0;; > - =C2=A0 =C2=A0v9) > - =C2=A0 =C2=A0 =C2=A0cpu=3D"sparc64" > - =C2=A0 =C2=A0;; > - =C2=A0 =C2=A0*) > - =C2=A0 =C2=A0 =C2=A0echo "undefined SPARC architecture. Exiting"; > - =C2=A0 =C2=A0 =C2=A0exit 1 > - =C2=A0 =C2=A0;; > - =C2=A0 =C2=A0esac > - =C2=A0;; > =C2=A0 esac > =C2=A0done > =C2=A0# OS specific > @@ -284,8 +268,6 @@ elif check_define __i386__ ; then > =C2=A0elif check_define __x86_64__ ; then > =C2=A0 cpu=3D"x86_64" > =C2=A0elif check_define __sparc__ ; then > - =C2=A0# We can't check for 64 bit (when gcc is biarch) or V8PLUSA > - =C2=A0# They must be specified using --sparc_cpu > =C2=A0 if check_define __arch64__ ; then > =C2=A0 =C2=A0 cpu=3D"sparc64" > =C2=A0 else > @@ -749,8 +731,6 @@ for opt do > =C2=A0 ;; > =C2=A0 --enable-uname-release=3D*) uname_release=3D"$optarg" > =C2=A0 ;; > - =C2=A0--sparc_cpu=3D*) > - =C2=A0;; > =C2=A0 --enable-werror) werror=3D"yes" > =C2=A0 ;; > =C2=A0 --disable-werror) werror=3D"no" > @@ -830,32 +810,19 @@ for opt do > =C2=A0 esac > =C2=A0done > > -# > -# If cpu ~=3D sparc and =C2=A0sparc_cpu hasn't been defined, plug in the= right > -# QEMU_CFLAGS/LDFLAGS (assume sparc_v8plus for 32-bit and sparc_v9 for 6= 4-bit) > -# > =C2=A0host_guest_base=3D"no" > =C2=A0case "$cpu" in > - =C2=A0 =C2=A0sparc) case $sparc_cpu in > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 v7|v8) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 QEMU_CFLAGS=3D"-mcpu=3D${spar= c_cpu} -D__sparc_${sparc_cpu}__ $QEMU_CFLAGS" > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ;; > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 v8plus|v8plusa) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 QEMU_CFLAGS=3D"-mcpu=3Dultras= parc -D__sparc_${sparc_cpu}__ $QEMU_CFLAGS" > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ;; > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *) # sparc_cpu not defined in the co= mmand line > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 QEMU_CFLAGS=3D"-mcpu=3Dultras= parc -D__sparc_v8plus__ $QEMU_CFLAGS" > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 esac > + =C2=A0 =C2=A0sparc) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0LDFLAGS=3D"-m32 $LDFLAGS" > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 QEMU_CFLAGS=3D"-m32 -ffixed-g2 -ffix= ed-g3 $QEMU_CFLAGS" > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 QEMU_CFLAGS=3D"-m32 -mcpu=3Dultraspa= rc $QEMU_CFLAGS" > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 QEMU_CFLAGS=3D"-ffixed-g2 -ffixed-g3= $QEMU_CFLAGS" > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if test "$solaris" =3D "no" ; th= en > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0QEMU_CFLAGS=3D"-ffixed-g1= -ffixed-g6 $QEMU_CFLAGS" > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 helper_cflags=3D"-ffixed-i0" > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fi > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0;; > =C2=A0 =C2=A0 sparc64) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 QEMU_CFLAGS=3D"-m64 -mcpu=3Dultraspa= rc -D__sparc_v9__ $QEMU_CFLAGS" > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0LDFLAGS=3D"-m64 $LDFLAGS" > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 QEMU_CFLAGS=3D"-m64 -mcpu=3Dultraspa= rc $QEMU_CFLAGS" > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0QEMU_CFLAGS=3D"-ffixed-g5 -ffixe= d-g6 -ffixed-g7 $QEMU_CFLAGS" > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if test "$solaris" !=3D "no" ; t= hen > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0QEMU_CFLAGS=3D"-ffixed-g1= $QEMU_CFLAGS" > diff --git a/disas.c b/disas.c > index 4945c44..b3434fa 100644 > --- a/disas.c > +++ b/disas.c > @@ -175,9 +175,7 @@ void target_disas(FILE *out, target_ulong code, targe= t_ulong size, int flags) > =C2=A0 =C2=A0 =C2=A0 =C2=A0print_insn =3D print_insn_arm; > =C2=A0#elif defined(TARGET_SPARC) > =C2=A0 =C2=A0 print_insn =3D print_insn_sparc; > -#ifdef TARGET_SPARC64 > =C2=A0 =C2=A0 disasm_info.mach =3D bfd_mach_sparc_v9b; > -#endif This is not OK, it would change ASI printout for V8 guest code. > =C2=A0#elif defined(TARGET_PPC) > =C2=A0 =C2=A0 if (flags >> 16) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 disasm_info.endian =3D BFD_ENDIAN_LITTLE; > @@ -287,9 +285,7 @@ void disas(FILE *out, void *code, unsigned long size) > =C2=A0 =C2=A0 print_insn =3D print_insn_alpha; > =C2=A0#elif defined(__sparc__) > =C2=A0 =C2=A0 print_insn =3D print_insn_sparc; > -#if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(_= _sparc_v9__) > =C2=A0 =C2=A0 disasm_info.mach =3D bfd_mach_sparc_v9b; > -#endif This change is OK, it's for Sparc V9 host. > =C2=A0#elif defined(__arm__) > =C2=A0 =C2=A0 print_insn =3D print_insn_arm; > =C2=A0#elif defined(__MIPSEB__) > @@ -397,9 +393,7 @@ void monitor_disas(Monitor *mon, CPUArchState *env, > =C2=A0 =C2=A0 print_insn =3D print_insn_alpha; > =C2=A0#elif defined(TARGET_SPARC) > =C2=A0 =C2=A0 print_insn =3D print_insn_sparc; > -#ifdef TARGET_SPARC64 > =C2=A0 =C2=A0 disasm_info.mach =3D bfd_mach_sparc_v9b; > -#endif This is again for the guest code disassembly (from monitor) which could be V8, so not OK. > =C2=A0#elif defined(TARGET_PPC) > =C2=A0#ifdef TARGET_PPC64 > =C2=A0 =C2=A0 disasm_info.mach =3D bfd_mach_ppc64; > diff --git a/dyngen-exec.h b/dyngen-exec.h > index 083e20b..cfeef99 100644 > --- a/dyngen-exec.h > +++ b/dyngen-exec.h > @@ -39,13 +39,11 @@ > =C2=A0#elif defined(__sparc__) > =C2=A0#ifdef CONFIG_SOLARIS > =C2=A0#define AREG0 "g2" > -#else > -#ifdef __sparc_v9__ > +#elif HOST_LONG_BITS =3D=3D 64 > =C2=A0#define AREG0 "g5" > =C2=A0#else > =C2=A0#define AREG0 "g6" > =C2=A0#endif > -#endif > =C2=A0#elif defined(__s390__) > =C2=A0#define AREG0 "r10" > =C2=A0#elif defined(__alpha__) > diff --git a/exec.c b/exec.c > index 6731ab8..ad13ce1 100644 > --- a/exec.c > +++ b/exec.c > @@ -86,7 +86,7 @@ static int nb_tbs; > =C2=A0/* any access to the tbs or the page table must use this lock */ > =C2=A0spinlock_t tb_lock =3D SPIN_LOCK_UNLOCKED; > > -#if defined(__arm__) || defined(__sparc_v9__) > +#if defined(__arm__) || defined(__sparc__) > =C2=A0/* The prologue must be reachable with a direct jump. ARM and Sparc= 64 > =C2=A0have limited branch ranges (possibly also PPC) so place it in a > =C2=A0section close to code segment. */ > @@ -559,10 +559,9 @@ static void code_gen_alloc(unsigned long tb_size) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Cannot map more than that */ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (code_gen_buffer_size > (800 * 1024 * 1024= )) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 code_gen_buffer_size =3D (800 *= 1024 * 1024); > -#elif defined(__sparc_v9__) > +#elif defined(__sparc__) && HOST_LONG_BITS =3D=3D 64 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 // Map the buffer below 2G, so we can use dir= ect calls and branches > - =C2=A0 =C2=A0 =C2=A0 =C2=A0flags |=3D MAP_FIXED; > - =C2=A0 =C2=A0 =C2=A0 =C2=A0start =3D (void *) 0x60000000UL; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0start =3D (void *) 0x40000000UL; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (code_gen_buffer_size > (512 * 1024 * 1024= )) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 code_gen_buffer_size =3D (512 *= 1024 * 1024); > =C2=A0#elif defined(__arm__) > @@ -600,10 +599,9 @@ static void code_gen_alloc(unsigned long tb_size) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Cannot map more than that */ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (code_gen_buffer_size > (800 * 1024 * 1024= )) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 code_gen_buffer_size =3D (800 *= 1024 * 1024); > -#elif defined(__sparc_v9__) > +#elif defined(__sparc__) && HOST_LONG_BITS =3D=3D 64 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 // Map the buffer below 2G, so we can use dir= ect calls and branches > - =C2=A0 =C2=A0 =C2=A0 =C2=A0flags |=3D MAP_FIXED; > - =C2=A0 =C2=A0 =C2=A0 =C2=A0addr =3D (void *) 0x60000000UL; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0addr =3D (void *) 0x40000000UL; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (code_gen_buffer_size > (512 * 1024 * 1024= )) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 code_gen_buffer_size =3D (512 *= 1024 * 1024); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > diff --git a/qemu-timer.h b/qemu-timer.h > index de17f3b..b730427 100644 > --- a/qemu-timer.h > +++ b/qemu-timer.h > @@ -221,7 +221,7 @@ static inline int64_t cpu_get_real_ticks(void) > =C2=A0 =C2=A0 return val; > =C2=A0} > > -#elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined= (__sparc_v9__) > +#elif defined(__sparc__) > > =C2=A0static inline int64_t cpu_get_real_ticks (void) > =C2=A0{ > @@ -230,6 +230,8 @@ static inline int64_t cpu_get_real_ticks (void) > =C2=A0 =C2=A0 asm volatile("rd %%tick,%0" : "=3Dr"(rval)); > =C2=A0 =C2=A0 return rval; > =C2=A0#else > + =C2=A0 =C2=A0/* We need an %o or %g register for this. =C2=A0For recent= enough gcc > + =C2=A0 =C2=A0 =C2=A0 there is an "h" constraint for that. =C2=A0Don't b= other with that. =C2=A0*/ > =C2=A0 =C2=A0 union { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint64_t i64; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct { > @@ -237,8 +239,8 @@ static inline int64_t cpu_get_real_ticks (void) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t low; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } =C2=A0 =C2=A0 =C2=A0 i32; > =C2=A0 =C2=A0 } rval; > - =C2=A0 =C2=A0asm volatile("rd %%tick,%1; srlx %1,32,%0" > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 : "=3Dr"(rval.i= 32.high), "=3Dr"(rval.i32.low)); > + =C2=A0 =C2=A0asm volatile("rd %%tick,%%g1; srlx %%g1,32,%0; mov %%g1,%1= " > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 : "=3Dr"(rval.i= 32.high), "=3Dr"(rval.i32.low) : : "g1"); > =C2=A0 =C2=A0 return rval.i64; > =C2=A0#endif > =C2=A0} > diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c > index 358a70c..38be0c8 100644 > --- a/tcg/sparc/tcg-target.c > +++ b/tcg/sparc/tcg-target.c > @@ -627,18 +627,10 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGC= ond cond, TCGArg ret, > > =C2=A0 =C2=A0 default: > =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_out_cmp(s, c1, c2, c2const); > -#if defined(__sparc_v9__) || defined(__sparc_v8plus__) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_out_movi_imm13(s, ret, 0); > - =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | INSN_R= S1(tcg_cond_to_bcond[cond]) > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | MOVCC_= ICC | INSN_IMM11(1)); > -#else > - =C2=A0 =C2=A0 =C2=A0 =C2=A0t =3D gen_new_label(); > - =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_= bcond[cond], 1), t); > - =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_movi_imm13(s, ret, 1); > - =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_movi_imm13(s, ret, 0); > - =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out_label(s, t, s->code_ptr); > -#endif > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_out32(s, ARITH_MOVCC | INSN_RD(ret) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| INSN_RS= 1(tcg_cond_to_bcond[cond]) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| MOVCC_I= CC | INSN_IMM11(1)); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 return; > =C2=A0 =C2=A0 } > > @@ -768,7 +760,7 @@ static const void * const qemu_st_helpers[4] =3D { > =C2=A0#endif > =C2=A0#endif > > -#ifdef __arch64__ > +#if TCG_TARGET_REG_BITS =3D=3D 64 > =C2=A0#define HOST_LD_OP LDX > =C2=A0#define HOST_ST_OP STX > =C2=A0#define HOST_SLL_OP SHIFT_SLLX > @@ -1630,11 +1622,9 @@ static void tcg_target_init(TCGContext *s) > > =C2=A0#if TCG_TARGET_REG_BITS =3D=3D 64 > =C2=A0# define ELF_HOST_MACHINE =C2=A0EM_SPARCV9 > -#elif defined(__sparc_v8plus__) > +#else > =C2=A0# define ELF_HOST_MACHINE =C2=A0EM_SPARC32PLUS > =C2=A0# define ELF_HOST_FLAGS =C2=A0 =C2=A0EF_SPARC_32PLUS > -#else > -# define ELF_HOST_MACHINE =C2=A0EM_SPARC > =C2=A0#endif > > =C2=A0typedef struct { > diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h > index ee2274d..56742bf 100644 > --- a/tcg/sparc/tcg-target.h > +++ b/tcg/sparc/tcg-target.h > @@ -67,7 +67,8 @@ typedef enum { > > =C2=A0/* used for function call generation */ > =C2=A0#define TCG_REG_CALL_STACK TCG_REG_I6 > -#ifdef __arch64__ > + > +#if TCG_TARGET_REG_BITS =3D=3D 64 > =C2=A0// Reserve space for AREG0 > =C2=A0#define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TCG_STATIC_CALL_ARGS_SI= ZE) > @@ -81,7 +82,7 @@ typedef enum { > =C2=A0#define TCG_TARGET_STACK_ALIGN 8 > =C2=A0#endif > > -#ifdef __arch64__ > +#if TCG_TARGET_REG_BITS =3D=3D 64 > =C2=A0#define TCG_TARGET_EXTEND_ARGS 1 > =C2=A0#endif > > @@ -128,7 +129,7 @@ typedef enum { > =C2=A0/* Note: must be synced with dyngen-exec.h */ > =C2=A0#ifdef CONFIG_SOLARIS > =C2=A0#define TCG_AREG0 TCG_REG_G2 > -#elif defined(__sparc_v9__) > +#elif HOST_LONG_BITS =3D=3D 64 > =C2=A0#define TCG_AREG0 TCG_REG_G5 > =C2=A0#else > =C2=A0#define TCG_AREG0 TCG_REG_G6 > diff --git a/tcg/tcg.c b/tcg/tcg.c > index ab589c7..9f234f4 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -1457,7 +1457,8 @@ static void temp_allocate_frame(TCGContext *s, int = temp) > =C2=A0{ > =C2=A0 =C2=A0 TCGTemp *ts; > =C2=A0 =C2=A0 ts =3D &s->temps[temp]; > -#ifndef __sparc_v9__ /* Sparc64 stack is accessed with offset of 2047 */ > +#if !(defined(__sparc__) && TCG_TARGET_REG_BITS =3D=3D 64) > + =C2=A0 =C2=A0/* Sparc64 stack is accessed with offset of 2047 */ > =C2=A0 =C2=A0 s->current_frame_offset =3D (s->current_frame_offset + > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(tcg_target_long)sizeof(tcg_target_lo= ng) - 1) & > =C2=A0 =C2=A0 =C2=A0 =C2=A0 ~(sizeof(tcg_target_long) - 1); > -- > 1.7.7.6 >