From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35641) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SghN1-0005dg-6L for qemu-devel@nongnu.org; Mon, 18 Jun 2012 15:12:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SghMx-0005ro-U2 for qemu-devel@nongnu.org; Mon, 18 Jun 2012 15:12:14 -0400 Received: from mail-yx0-f173.google.com ([209.85.213.173]:34388) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SghMx-0005rj-LF for qemu-devel@nongnu.org; Mon, 18 Jun 2012 15:12:11 -0400 Received: by yenl1 with SMTP id l1so3925556yen.4 for ; Mon, 18 Jun 2012 12:12:09 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1339981384-9117-1-git-send-email-proljc@gmail.com> References: <1339981384-9117-1-git-send-email-proljc@gmail.com> From: Blue Swirl Date: Mon, 18 Jun 2012 19:11:48 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v5 00/16] QEMU OpenRISC support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jia Liu Cc: qemu-devel@nongnu.org On Mon, Jun 18, 2012 at 1:02 AM, Jia Liu wrote: > This is the OpenCores OpenRISC 1200 support for QEMU. > Full implementation of the system-model and linux-user-model support. > > OpenRISC 1200 is a OpenCores open source CPU, > its architecture manual can be found at > http://opencores.org/svnget,or1k?file=3D/trunk/docs/openrisc_arch.pdf > > A OpenRISC Linux kernel contain initramfs for qemu-system-or32 testing > can be found at > https://docs.google.com/file/d/0BxeTrz3x0CBLSjR3Sk5Vd3h1eDA/edit?pli=3D1 > > A OpenRISC hello-world program for qemu-or32 testing can be found at > https://docs.google.com/file/d/0BxeTrz3x0CBLN3RSWUFNYktrU2M/edit?pli=3D1 > > Signed-off-by: Jia Liu I had minor comments to a few patches, others looked ready. Please still check the patches with scripts/checkpatch.pl. > --- > > Version History: > V5: > Addressed Blue's review comments: > - reimplement l.mul* l.mfspr l.add* l.sub* and more. > - shoot bugs with "--enable-debug-tcg" > > V4: > Addressed Max's review comments: > - fix l.div l.mac* l.mul*, and more. > > Addressed Richard, Wei-Ren and Andreas's review comments: > - replace tcg_temp_new_i32 with tcg_temp_local_new_i32 in l.div translati= on. > > Addressed Andreas's review comments: > - update to suit Makefile system. > > - add UPR CPUCFGR and MMUCFGR impelement. > - add instruction check functions. > > Version History: > V3: > Addressed Stefan and Andreas's review comments: > - use QEMU and OpenRISC's official name. > > Addressed Andreas's review comments: > - reimplement cpu QOM. > - combine target stubs and QOM implement. > - use new commit message and subject. > > Addressed Max's review comments: > - handle div zero exception. > - reimplement float point instructions. > - fix l.mac*, l.mul*, and more. > > V2: > Addressed Malc, Weiren, Andreas and Blue's review comments: > - reimplement cpu QOM. > > Addressed Andreas's review comments: > - reimplement machine. > - rewrite the Copyright Notice using better format. > > Addressed Blue and Weiren's review comments: > - compiling with AREG0 and remove global env, no dyngen-exe longer. > > Addressed Max, Blue and Weiren's review comments: > - handle div zero exception. > - handle illegal instruction. > > Addressed Blue's review comments: > - separate do_interrupt into intrpt.c form intrpt_helper.c. > - add QEMU_NORETURN to raise_exception. > - reimplement float instrutions. > - fix type of linux syscall and termbits. > - reimplement sim board. > - use the LGPL web URL in Copyright Notice. > - reimplemt branch instructions. > > - split taregt stubs, QOM and machine. > > V1: > - add QEMU OpenRISC support. > - well tested on x64 machine, and final tested x86 machine. > > Jia Liu (16): > =C2=A0target-or32: Add target stubs and cpu support > =C2=A0target-or32: Add target machine > =C2=A0target-or32: Add MMU support > =C2=A0target-or32: Add interrupt support > =C2=A0target-or32: Add exception support > =C2=A0target-or32: Add int instruction helpers > =C2=A0target-or32: Add float instruction helpers > =C2=A0target-or32: Add translation routines > =C2=A0target-or32: Add PIC support > =C2=A0target-or32: Add timer support > =C2=A0target-or32: Add a IIS dummy board > =C2=A0target-or32: Add system instructions > =C2=A0target-or32: Add gdb stub support > =C2=A0target-or32: Add linux syscall, signal and termbits > =C2=A0target-or32: Add linux user support > =C2=A0target-or32: Add testcases > > =C2=A0arch_init.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A02 + > =C2=A0arch_init.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A01 + > =C2=A0configure =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 15 +- > =C2=A0cpu-exec.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 19 + > =C2=A0default-configs/or32-linux-user.mak | =C2=A0 =C2=A02 + > =C2=A0default-configs/or32-softmmu.mak =C2=A0 =C2=A0| =C2=A0 =C2=A06 + > =C2=A0elf.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A02 + > =C2=A0gdbstub.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 64 ++ > =C2=A0hw/openrisc/Makefile.objs =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2= =A0 =C2=A03 + > =C2=A0hw/openrisc_cpudev.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0| =C2=A0 29 + > =C2=A0hw/openrisc_pic.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 | =C2=A0 78 ++ > =C2=A0hw/openrisc_sim.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 | =C2=A0145 +++ > =C2=A0hw/openrisc_timer.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | =C2=A0160 +++ > =C2=A0linux-user/elfload.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0| =C2=A0 41 + > =C2=A0linux-user/main.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 | =C2=A0100 ++ > =C2=A0linux-user/openrisc/syscall.h =C2=A0 =C2=A0 =C2=A0 | =C2=A0 24 + > =C2=A0linux-user/openrisc/syscall_nr.h =C2=A0 =C2=A0| =C2=A0506 +++++++++ > =C2=A0linux-user/openrisc/target_signal.h | =C2=A0 26 + > =C2=A0linux-user/openrisc/termbits.h =C2=A0 =C2=A0 =C2=A0| =C2=A0294 ++++= + > =C2=A0linux-user/signal.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | =C2=A0229 ++++ > =C2=A0linux-user/syscall.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0| =C2=A0 =C2=A02 +- > =C2=A0linux-user/syscall_defs.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2= =A0 40 +- > =C2=A0poison.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A01 + > =C2=A0target-openrisc/Makefile.objs =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A04= + > =C2=A0target-openrisc/cpu.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 | =C2=A0240 +++++ > =C2=A0target-openrisc/cpu.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 | =C2=A0445 ++++++++ > =C2=A0target-openrisc/excp.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| =C2=A0 27 + > =C2=A0target-openrisc/excp.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| =C2=A0 28 + > =C2=A0target-openrisc/excp_helper.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0 27 + > =C2=A0target-openrisc/fpu_helper.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0275= +++++ > =C2=A0target-openrisc/helper.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 69 ++ > =C2=A0target-openrisc/int_helper.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 51= + > =C2=A0target-openrisc/intrpt.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 74 ++ > =C2=A0target-openrisc/intrpt_helper.c =C2=A0 =C2=A0 | =C2=A0 52 + > =C2=A0target-openrisc/machine.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2= =A0 50 + > =C2=A0target-openrisc/mmu.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 | =C2=A0236 ++++ > =C2=A0target-openrisc/mmu_helper.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 63= ++ > =C2=A0target-openrisc/sys_helper.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0233= ++++ > =C2=A0target-openrisc/translate.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 2036 ++++= +++++++++++++++++++++++++++++++ > =C2=A0tests/tcg/openrisc/Makefile =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 71= ++ > =C2=A0tests/tcg/openrisc/test_add.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0 34 + > =C2=A0tests/tcg/openrisc/test_addc.c =C2=A0 =C2=A0 =C2=A0| =C2=A0 39 + > =C2=A0tests/tcg/openrisc/test_addi.c =C2=A0 =C2=A0 =C2=A0| =C2=A0 31 + > =C2=A0tests/tcg/openrisc/test_addic.c =C2=A0 =C2=A0 | =C2=A0 33 + > =C2=A0tests/tcg/openrisc/test_and_or.c =C2=A0 =C2=A0| =C2=A0 61 ++ > =C2=A0tests/tcg/openrisc/test_bf.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 46= + > =C2=A0tests/tcg/openrisc/test_bnf.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0 50 + > =C2=A0tests/tcg/openrisc/test_div.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0 32 + > =C2=A0tests/tcg/openrisc/test_divu.c =C2=A0 =C2=A0 =C2=A0| =C2=A0 32 + > =C2=A0tests/tcg/openrisc/test_extx.c =C2=A0 =C2=A0 =C2=A0| =C2=A0 72 ++ > =C2=A0tests/tcg/openrisc/test_fx.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 53= + > =C2=A0tests/tcg/openrisc/test_j.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 26= + > =C2=A0tests/tcg/openrisc/test_jal.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0 26 + > =C2=A0tests/tcg/openrisc/test_lf_add.c =C2=A0 =C2=A0| =C2=A0 39 + > =C2=A0tests/tcg/openrisc/test_lf_div.c =C2=A0 =C2=A0| =C2=A0 34 + > =C2=A0tests/tcg/openrisc/test_lf_eqs.c =C2=A0 =C2=A0| =C2=A0 84 ++ > =C2=A0tests/tcg/openrisc/test_lf_ges.c =C2=A0 =C2=A0| =C2=A0 84 ++ > =C2=A0tests/tcg/openrisc/test_lf_gts.c =C2=A0 =C2=A0| =C2=A0 84 ++ > =C2=A0tests/tcg/openrisc/test_lf_les.c =C2=A0 =C2=A0| =C2=A0 84 ++ > =C2=A0tests/tcg/openrisc/test_lf_lts.c =C2=A0 =C2=A0| =C2=A0 91 ++ > =C2=A0tests/tcg/openrisc/test_lf_mul.c =C2=A0 =C2=A0| =C2=A0 22 + > =C2=A0tests/tcg/openrisc/test_lf_nes.c =C2=A0 =C2=A0| =C2=A0 87 ++ > =C2=A0tests/tcg/openrisc/test_lf_rem.c =C2=A0 =C2=A0| =C2=A0 32 + > =C2=A0tests/tcg/openrisc/test_lf_sub.c =C2=A0 =C2=A0| =C2=A0 33 + > =C2=A0tests/tcg/openrisc/test_logic.c =C2=A0 =C2=A0 | =C2=A0100 ++ > =C2=A0tests/tcg/openrisc/test_lx.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 78= ++ > =C2=A0tests/tcg/openrisc/test_movhi.c =C2=A0 =C2=A0 | =C2=A0 30 + > =C2=A0tests/tcg/openrisc/test_mul.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0 47 + > =C2=A0tests/tcg/openrisc/test_muli.c =C2=A0 =C2=A0 =C2=A0| =C2=A0 47 + > =C2=A0tests/tcg/openrisc/test_mulu.c =C2=A0 =C2=A0 =C2=A0| =C2=A0 47 + > =C2=A0tests/tcg/openrisc/test_sfeq.c =C2=A0 =C2=A0 =C2=A0| =C2=A0 44 + > =C2=A0tests/tcg/openrisc/test_sfeqi.c =C2=A0 =C2=A0 | =C2=A0 39 + > =C2=A0tests/tcg/openrisc/test_sfges.c =C2=A0 =C2=A0 | =C2=A0 44 + > =C2=A0tests/tcg/openrisc/test_sfgesi.c =C2=A0 =C2=A0| =C2=A0 40 + > =C2=A0tests/tcg/openrisc/test_sfgeu.c =C2=A0 =C2=A0 | =C2=A0 44 + > =C2=A0tests/tcg/openrisc/test_sfgeui.c =C2=A0 =C2=A0| =C2=A0 41 + > =C2=A0tests/tcg/openrisc/test_sfgts.c =C2=A0 =C2=A0 | =C2=A0 45 + > =C2=A0tests/tcg/openrisc/test_sfgtsi.c =C2=A0 =C2=A0| =C2=A0 41 + > =C2=A0tests/tcg/openrisc/test_sfgtu.c =C2=A0 =C2=A0 | =C2=A0 43 + > =C2=A0tests/tcg/openrisc/test_sfgtui.c =C2=A0 =C2=A0| =C2=A0 42 + > =C2=A0tests/tcg/openrisc/test_sfles.c =C2=A0 =C2=A0 | =C2=A0 26 + > =C2=A0tests/tcg/openrisc/test_sflesi.c =C2=A0 =C2=A0| =C2=A0 39 + > =C2=A0tests/tcg/openrisc/test_sfleu.c =C2=A0 =C2=A0 | =C2=A0 43 + > =C2=A0tests/tcg/openrisc/test_sfleui.c =C2=A0 =C2=A0| =C2=A0 39 + > =C2=A0tests/tcg/openrisc/test_sflts.c =C2=A0 =C2=A0 | =C2=A0 43 + > =C2=A0tests/tcg/openrisc/test_sfltsi.c =C2=A0 =C2=A0| =C2=A0 38 + > =C2=A0tests/tcg/openrisc/test_sfltu.c =C2=A0 =C2=A0 | =C2=A0 41 + > =C2=A0tests/tcg/openrisc/test_sfltui.c =C2=A0 =C2=A0| =C2=A0 39 + > =C2=A0tests/tcg/openrisc/test_sfne.c =C2=A0 =C2=A0 =C2=A0| =C2=A0 43 + > =C2=A0tests/tcg/openrisc/test_sfnei.c =C2=A0 =C2=A0 | =C2=A0 38 + > =C2=A0tests/tcg/openrisc/test_sub.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0 34 + > =C2=A091 files changed, 8168 insertions(+), 6 deletions(-) > =C2=A0create mode 100644 default-configs/or32-linux-user.mak > =C2=A0create mode 100644 default-configs/or32-softmmu.mak > =C2=A0create mode 100644 hw/openrisc/Makefile.objs > =C2=A0create mode 100644 hw/openrisc_cpudev.h > =C2=A0create mode 100644 hw/openrisc_pic.c > =C2=A0create mode 100644 hw/openrisc_sim.c > =C2=A0create mode 100644 hw/openrisc_timer.c > =C2=A0create mode 100644 linux-user/openrisc/syscall.h > =C2=A0create mode 100644 linux-user/openrisc/syscall_nr.h > =C2=A0create mode 100644 linux-user/openrisc/target_signal.h > =C2=A0create mode 100644 linux-user/openrisc/termbits.h > =C2=A0create mode 100644 target-openrisc/Makefile.objs > =C2=A0create mode 100644 target-openrisc/cpu.c > =C2=A0create mode 100644 target-openrisc/cpu.h > =C2=A0create mode 100644 target-openrisc/excp.c > =C2=A0create mode 100644 target-openrisc/excp.h > =C2=A0create mode 100644 target-openrisc/excp_helper.c > =C2=A0create mode 100644 target-openrisc/fpu_helper.c > =C2=A0create mode 100644 target-openrisc/helper.h > =C2=A0create mode 100644 target-openrisc/int_helper.c > =C2=A0create mode 100644 target-openrisc/intrpt.c > =C2=A0create mode 100644 target-openrisc/intrpt_helper.c > =C2=A0create mode 100644 target-openrisc/machine.c > =C2=A0create mode 100644 target-openrisc/mmu.c > =C2=A0create mode 100644 target-openrisc/mmu_helper.c > =C2=A0create mode 100644 target-openrisc/sys_helper.c > =C2=A0create mode 100644 target-openrisc/translate.c > =C2=A0create mode 100644 tests/tcg/openrisc/Makefile > =C2=A0create mode 100644 tests/tcg/openrisc/test_add.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_addc.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_addi.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_addic.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_and_or.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_bf.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_bnf.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_div.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_divu.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_extx.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_fx.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_j.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_jal.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_add.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_div.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_eqs.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_ges.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_gts.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_les.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_lts.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_mul.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_nes.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_rem.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lf_sub.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_logic.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_lx.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_movhi.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_mul.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_muli.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_mulu.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfeq.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfeqi.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfges.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfgesi.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfgeu.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfgeui.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfgts.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfgtsi.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfgtu.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfgtui.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfles.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sflesi.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfleu.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfleui.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sflts.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfltsi.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfltu.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfltui.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfne.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sfnei.c > =C2=A0create mode 100644 tests/tcg/openrisc/test_sub.c > > -- > 1.7.9.5 > >