From: Michael Goffioul <michael.goffioul@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>,
QEMU Developers <qemu-devel@nongnu.org>,
qemu-discuss <qemu-discuss@nongnu.org>
Subject: Re: Invalid ARM instruction for clang-compiled Android code
Date: Fri, 15 Nov 2019 09:01:15 -0500 [thread overview]
Message-ID: <CAB-99LsMY5R11VN=2aOq0CDcvm5sN5rTjCAZumOsZ-uWjXgujQ@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA-RXurz2OB24i1wypumCDWf5s__mC33mFzBA3SCsm4_VA@mail.gmail.com>
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On Fri, Nov 15, 2019 at 6:03 AM Peter Maydell <peter.maydell@linaro.org>
wrote:
> Richard, I think we're tripping over the check you added
> in commit af2882289951e. Specifically:
>
> + /* We UNDEF for these UNPREDICTABLE cases. */
> + if (a->rd == 15 || a->rn == 15 || a->rt == 15
> + || a->rd == a->rn || a->rd == a->rt
> + || (s->thumb && (a->rd == 13 || a->rt == 13))
> + || (mop == MO_64
> + && (a->rt2 == 15
> + || a->rd == a->rt2 || a->rt == a->rt2
> + || (s->thumb && a->rt2 == 13)))) {
> + unallocated_encoding(s);
> + return true;
> + }
>
> in the mop == MO_64 subclause we check for
> a->rt == a->rt2
> so we will UNDEF for rt == rt2, as in this example. But the
> pseudocode in the spec doesn't say that rt == rt2 is
> an UNPREDICTABLE case. (It is an UNDPREDICTABLE
> case for LDREXD, but STREXD lets you write the same
> register twice if you want to.) Or am I misreading this?
>
BTW, I can confirm that removing the check "a->rt == a->rt2" seems to fix
my problem.
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next prev parent reply other threads:[~2019-11-15 15:04 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAB-99Lv3LySps4MOoKEj7Sp0CBouv-KgZp2osbiokSq_Gdfj5Q@mail.gmail.com>
2019-11-15 11:03 ` Invalid ARM instruction for clang-compiled Android code Peter Maydell
2019-11-15 11:58 ` Michael Goffioul
2019-11-15 14:01 ` Michael Goffioul [this message]
2019-11-17 8:45 ` Richard Henderson
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