From: Yubin Zou <yubinz@google.com>
To: "Cédric Le Goater" <clg@redhat.com>
Cc: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
Steven Lee <steven_lee@aspeedtech.com>,
Troy Lee <leetroy@gmail.com>,
Jamin Lin <jamin_lin@aspeedtech.com>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
Joel Stanley <joel@jms.id.au>, Fabiano Rosas <farosas@suse.de>,
Laurent Vivier <lvivier@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Kane-Chen-AS <kane_chen@aspeedtech.com>,
Nabih Estefan <nabihestefan@google.com>,
qemu-arm@nongnu.org
Subject: Re: [PATCH v2 2/6] hw/gpio/aspeed_sgpio: aspeed: Add QOM property accessors for SGPIO pins
Date: Wed, 10 Dec 2025 00:08:52 -0800 [thread overview]
Message-ID: <CABU_6B+vRgWyEifCc4h1fJUPduRK68W44koVxRYGkeuHGEpLgg@mail.gmail.com> (raw)
In-Reply-To: <4dae8293-066f-4354-b50a-05ba4cc9b80f@redhat.com>
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Hi Cédric
Good catch. I will fix these issues.
Yubin
On Tue, Dec 9, 2025 at 6:52 AM Cédric Le Goater <clg@redhat.com> wrote:
> Hi,
>
> The subject needs a fix. Please remove the extra 'aspeed: '.
>
> On 12/9/25 01:01, Yubin Zou wrote:
> > This commit adds QOM property accessors for the Aspeed SGPIO pins.
>
> I think you can drop the above sentence from the commit log. It's
> redundant with the subject.
>
> > The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are
> > implemented to get and set the level of individual SGPIO pins. These
> > are then exposed as boolean properties on the SGPIO device object.
> >
> > Signed-off-by: Yubin Zou <yubinz@google.com>
> > ---
> > hw/gpio/aspeed_sgpio.c | 78
> ++++++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 78 insertions(+)
> >
> > diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c
> > index
> 8676fa7ced134f1f62dc9e30b42c5fe6db3de268..efa7e574abe87e33e58ac88dba5e3469c6702b83
> 100644
> > --- a/hw/gpio/aspeed_sgpio.c
> > +++ b/hw/gpio/aspeed_sgpio.c
> > @@ -91,6 +91,73 @@ static void aspeed_sgpio_2700_write(void *opaque,
> hwaddr offset, uint64_t data,
> > }
> > }
> >
> > +static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin)
> > +{
> > + uint32_t value = s->ctrl_regs[pin >> 1];
> > + bool is_input = !(pin % 2);
> > + uint32_t bit_mask = 0;
> > +
> > + if (is_input) {
> > + bit_mask = SGPIO_SERIAL_IN_VAL_MASK;
> > + } else {
> > + bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;
> > + }
> > +
> > + return value & bit_mask;
> > +}
> > +
> > +static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin,
> bool level)
> > +{
> > + uint32_t value = s->ctrl_regs[pin >> 1];
> > + bool is_input = !(pin % 2);
> > + uint32_t bit_mask = 0;
> > +
> > + if (is_input) {
> > + bit_mask = SGPIO_SERIAL_IN_VAL_MASK;
> > + } else {
> > + bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;
> > + }
> > +
> > + if (level) {
> > + value |= bit_mask;
> > + } else {
> > + value &= ~bit_mask;
> > + }
> > + s->ctrl_regs[pin >> 1] = value;
> > +}
> > +
> > +static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char
> *name,
> > + void *opaque, Error **errp)
> > +{
> > + bool level = true;
> > + int pin = 0xfff;
> > + AspeedSGPIOState *s = ASPEED_SGPIO(obj);
> > +
> > + if (sscanf(name, "sgpio%d", &pin) != 1) {
> > + error_setg(errp, "%s: error reading %s", __func__, name);
> > + return;
> > + }
> > + level = aspeed_sgpio_get_pin_level(s, pin);
> > + visit_type_bool(v, name, &level, errp);
> > +}
> > +
> > +static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char
> *name,
> > + void *opaque, Error **errp)
> > +{
> > + bool level;
> > + int pin = 0xfff;
> > + AspeedSGPIOState *s = ASPEED_SGPIO(obj);
> > +
> > + if (!visit_type_bool(v, name, &level, errp)) {
> > + return;
> > + }
> > + if (sscanf(name, "sgpio%d", &pin) != 1) {
> > + error_setg(errp, "%s: error reading %s", __func__, name);
> > + return;
> > + }
> > + aspeed_sgpio_set_pin_level(s, pin, level);
> > +}
> > +
> > static const MemoryRegionOps aspeed_gpio_2700_ops = {
> > .read = aspeed_sgpio_2700_read,
> > .write = aspeed_sgpio_2700_write,
> > @@ -114,6 +181,16 @@ static void aspeed_sgpio_realize(DeviceState *dev,
> Error **errp)
> > sysbus_init_mmio(sbd, &s->iomem);
> > }
> >
> > +static void aspeed_sgpio_init(Object *obj)
> > +{
> > + for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) {
> > + char *name = g_strdup_printf("sgpio%d", i);
>
> You could use a g_autofree variable and drop the g_free below.
>
> How about using a "%03d" format in the printf and sscanf too ?
>
> C.
>
> > + object_property_add(obj, name, "bool", aspeed_sgpio_get_pin,
> > + aspeed_sgpio_set_pin, NULL, NULL);
> > + g_free(name);
> > + }
> > +}
> > +
> > static void aspeed_sgpio_class_init(ObjectClass *klass, const void
> *data)
> > {
> > DeviceClass *dc = DEVICE_CLASS(klass);
> > @@ -143,6 +220,7 @@ static const TypeInfo aspeed_sgpio_ast2700_info = {
> > .name = TYPE_ASPEED_SGPIO "-ast2700",
> > .parent = TYPE_ASPEED_SGPIO,
> > .class_init = aspeed_sgpio_2700_class_init,
> > + .instance_init = aspeed_sgpio_init,
> > };
> >
> > static void aspeed_sgpio_register_types(void)
> >
>
>
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next prev parent reply other threads:[~2025-12-10 8:09 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-09 0:01 [PATCH v2 0/6] hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO (SGPIO) controller model Yubin Zou
2025-12-09 0:01 ` [PATCH v2 1/6] hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO Yubin Zou
2025-12-09 9:22 ` Cédric Le Goater
2025-12-10 8:02 ` Yubin Zou
2025-12-09 0:01 ` [PATCH v2 2/6] hw/gpio/aspeed_sgpio: aspeed: Add QOM property accessors for SGPIO pins Yubin Zou
2025-12-09 14:52 ` Cédric Le Goater
2025-12-10 8:08 ` Yubin Zou [this message]
2025-12-09 0:01 ` [PATCH v2 3/6] hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling Yubin Zou
2025-12-09 0:01 ` [PATCH v2 4/6] hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers Yubin Zou
2025-12-09 16:15 ` Cédric Le Goater
2025-12-09 0:01 ` [PATCH v2 5/6] hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC Yubin Zou
2025-12-09 16:15 ` Cédric Le Goater
2025-12-09 0:01 ` [PATCH v2 6/6] test/qtest: Add Unit test for Aspeed SGPIO Yubin Zou
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