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From: =?UTF-8?Q?Marcin_Krzemi=C5=84ski?= <mar.krzeminski@gmail.com>
Date: Mon, 4 Jul 2016 09:12:09 +0200
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Subject: Re: [Qemu-devel] [PATCH v5 6/9] ast2400: add SMC controllers (FMC
 and SPI)
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To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>
Cc: Peter Maydell <peter.maydell@linaro.org>, Peter Crosthwaite <crosthwaite.peter@gmail.com>, kwolf@redhat.com, Andrew Jeffery <andrew@aj.id.au>, qemu-arm@nongnu.org, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, armbru@redhat.com

2016-07-04 8:58 GMT+02:00 C=C3=A9dric Le Goater <clg@kaod.org>:

> Hello Marcin,
>
> On 07/02/2016 07:00 PM, mar.krzeminski wrote:
> >>
> >> +
> >> +/* CE Control Register */
> >> +#define R_CE_CTRL            (0x04 / 4)
> >> +#define   CTRL_EXTENDED4       4  /* 32 bit addressing for SPI */
> >> +#define   CTRL_EXTENDED3       3  /* 32 bit addressing for SPI */
> >> +#define   CTRL_EXTENDED2       2  /* 32 bit addressing for SPI */
> >> +#define   CTRL_EXTENDED1       1  /* 32 bit addressing for SPI */
> >> +#define   CTRL_EXTENDED0       0  /* 32 bit addressing for SPI */
> > Hi
> >
> > Above comments does not say anything.
> >
>
> I suppose you mean that the names are confusing ?
>
> The default setting for CE0 and CE1 is done with the hardware strapping
> SCU70 register.
>
> Yes, is hard to say what does it mean and what it does (at least for me).
This is a minor.

Thanks,
Marcin

Thanks,
>
> C.
>
>