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Tue, 06 Jul 2021 23:51:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxgV7TX7itrkYhqGwIWfl1vnL5M6DN6Gx0AFjquD2Vr1z4BRlG5LuBcckSdl8OV3e+cdt0ktarMAuZk2C/EWMI= X-Received: by 2002:a63:5cb:: with SMTP id 194mr24442331pgf.146.1625640680370; Tue, 06 Jul 2021 23:51:20 -0700 (PDT) MIME-Version: 1.0 References: <20210705104632.2902400-1-david.edmondson@oracle.com> <20210705104632.2902400-9-david.edmondson@oracle.com> <0d75c3ab-926b-d4cd-244a-8c8b603535f9@linaro.org> In-Reply-To: <0d75c3ab-926b-d4cd-244a-8c8b603535f9@linaro.org> From: Paolo Bonzini Date: Wed, 7 Jul 2021 08:51:08 +0200 Message-ID: Subject: Re: [RFC PATCH 8/8] target/i386: Move X86XSaveArea into TCG To: Richard Henderson Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: multipart/alternative; boundary="0000000000004940f005c682f785" Received-SPF: pass client-ip=216.205.24.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.442, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm , Michael Roth , Marcelo Tosatti , qemu-devel , Cameron Esfahani , David Edmondson , Babu Moger , Roman Bolshakov Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000004940f005c682f785 Content-Type: text/plain; charset="UTF-8" Migration from KVM to TCG is broken anyway. The changing offsets do break migration of a KVM guest from Intel to AMD or vice versa, because of the difference in CPUID. That however is not changed by this patch. Paolo Il mer 7 lug 2021, 03:09 Richard Henderson ha scritto: > On 7/5/21 3:46 AM, David Edmondson wrote: > > Given that TCG is now the only consumer of X86XSaveArea, move the > > structure definition and associated offset declarations and checks to a > > TCG specific header. > > > > Signed-off-by: David Edmondson > > --- > > target/i386/cpu.h | 57 ------------------------------------ > > target/i386/tcg/fpu_helper.c | 1 + > > target/i386/tcg/tcg-cpu.h | 57 ++++++++++++++++++++++++++++++++++++ > > 3 files changed, 58 insertions(+), 57 deletions(-) > > > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > > index 96b672f8bd..0f7ddbfeae 100644 > > --- a/target/i386/cpu.h > > +++ b/target/i386/cpu.h > > @@ -1305,48 +1305,6 @@ typedef struct XSavePKRU { > > uint32_t padding; > > } XSavePKRU; > > > > -#define XSAVE_FCW_FSW_OFFSET 0x000 > > -#define XSAVE_FTW_FOP_OFFSET 0x004 > > -#define XSAVE_CWD_RIP_OFFSET 0x008 > > -#define XSAVE_CWD_RDP_OFFSET 0x010 > > -#define XSAVE_MXCSR_OFFSET 0x018 > > -#define XSAVE_ST_SPACE_OFFSET 0x020 > > -#define XSAVE_XMM_SPACE_OFFSET 0x0a0 > > -#define XSAVE_XSTATE_BV_OFFSET 0x200 > > -#define XSAVE_AVX_OFFSET 0x240 > > -#define XSAVE_BNDREG_OFFSET 0x3c0 > > -#define XSAVE_BNDCSR_OFFSET 0x400 > > -#define XSAVE_OPMASK_OFFSET 0x440 > > -#define XSAVE_ZMM_HI256_OFFSET 0x480 > > -#define XSAVE_HI16_ZMM_OFFSET 0x680 > > -#define XSAVE_PKRU_OFFSET 0xa80 > > - > > -typedef struct X86XSaveArea { > > - X86LegacyXSaveArea legacy; > > - X86XSaveHeader header; > > - > > - /* Extended save areas: */ > > - > > - /* AVX State: */ > > - XSaveAVX avx_state; > > - > > - /* Ensure that XSaveBNDREG is properly aligned. */ > > - uint8_t padding[XSAVE_BNDREG_OFFSET > > - - sizeof(X86LegacyXSaveArea) > > - - sizeof(X86XSaveHeader) > > - - sizeof(XSaveAVX)]; > > - > > - /* MPX State: */ > > - XSaveBNDREG bndreg_state; > > - XSaveBNDCSR bndcsr_state; > > - /* AVX-512 State: */ > > - XSaveOpmask opmask_state; > > - XSaveZMM_Hi256 zmm_hi256_state; > > - XSaveHi16_ZMM hi16_zmm_state; > > - /* PKRU State: */ > > - XSavePKRU pkru_state; > > -} X86XSaveArea; > > - > > QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); > > QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); > > QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); > > @@ -1355,21 +1313,6 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != > 0x200); > > QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); > > QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); > > > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fcw) != > XSAVE_FCW_FSW_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.ftw) != > XSAVE_FTW_FOP_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpip) != > XSAVE_CWD_RIP_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpdp) != > XSAVE_CWD_RDP_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.mxcsr) != > XSAVE_MXCSR_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpregs) != > XSAVE_ST_SPACE_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.xmm_regs) != > XSAVE_XMM_SPACE_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != > XSAVE_AVX_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != > XSAVE_BNDREG_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != > XSAVE_BNDCSR_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != > XSAVE_OPMASK_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != > XSAVE_ZMM_HI256_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != > XSAVE_HI16_ZMM_OFFSET); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != > XSAVE_PKRU_OFFSET); > > - > > typedef struct ExtSaveArea { > > uint32_t feature, bits; > > uint32_t offset, size; > > diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c > > index 4e11965067..74bbe94b80 100644 > > --- a/target/i386/tcg/fpu_helper.c > > +++ b/target/i386/tcg/fpu_helper.c > > @@ -20,6 +20,7 @@ > > #include "qemu/osdep.h" > > #include > > #include "cpu.h" > > +#include "tcg-cpu.h" > > #include "exec/helper-proto.h" > > #include "fpu/softfloat.h" > > #include "fpu/softfloat-macros.h" > > diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h > > index 36bd300af0..53a8494455 100644 > > --- a/target/i386/tcg/tcg-cpu.h > > +++ b/target/i386/tcg/tcg-cpu.h > > @@ -19,6 +19,63 @@ > > #ifndef TCG_CPU_H > > #define TCG_CPU_H > > > > +#define XSAVE_FCW_FSW_OFFSET 0x000 > > +#define XSAVE_FTW_FOP_OFFSET 0x004 > > +#define XSAVE_CWD_RIP_OFFSET 0x008 > > +#define XSAVE_CWD_RDP_OFFSET 0x010 > > +#define XSAVE_MXCSR_OFFSET 0x018 > > +#define XSAVE_ST_SPACE_OFFSET 0x020 > > +#define XSAVE_XMM_SPACE_OFFSET 0x0a0 > > +#define XSAVE_XSTATE_BV_OFFSET 0x200 > > +#define XSAVE_AVX_OFFSET 0x240 > > +#define XSAVE_BNDREG_OFFSET 0x3c0 > > +#define XSAVE_BNDCSR_OFFSET 0x400 > > +#define XSAVE_OPMASK_OFFSET 0x440 > > +#define XSAVE_ZMM_HI256_OFFSET 0x480 > > +#define XSAVE_HI16_ZMM_OFFSET 0x680 > > +#define XSAVE_PKRU_OFFSET 0xa80 > > + > > +typedef struct X86XSaveArea { > > + X86LegacyXSaveArea legacy; > > + X86XSaveHeader header; > > + > > + /* Extended save areas: */ > > + > > + /* AVX State: */ > > + XSaveAVX avx_state; > > + > > + /* Ensure that XSaveBNDREG is properly aligned. */ > > + uint8_t padding[XSAVE_BNDREG_OFFSET > > + - sizeof(X86LegacyXSaveArea) > > + - sizeof(X86XSaveHeader) > > + - sizeof(XSaveAVX)]; > > + > > + /* MPX State: */ > > + XSaveBNDREG bndreg_state; > > + XSaveBNDCSR bndcsr_state; > > + /* AVX-512 State: */ > > + XSaveOpmask opmask_state; > > + XSaveZMM_Hi256 zmm_hi256_state; > > + XSaveHi16_ZMM hi16_zmm_state; > > + /* PKRU State: */ > > + XSavePKRU pkru_state; > > +} X86XSaveArea; > > + > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fcw) != > XSAVE_FCW_FSW_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.ftw) != > XSAVE_FTW_FOP_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpip) != > XSAVE_CWD_RIP_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpdp) != > XSAVE_CWD_RDP_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.mxcsr) != > XSAVE_MXCSR_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpregs) != > XSAVE_ST_SPACE_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.xmm_regs) != > XSAVE_XMM_SPACE_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != > XSAVE_AVX_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != > XSAVE_BNDREG_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != > XSAVE_BNDCSR_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != > XSAVE_OPMASK_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != > XSAVE_ZMM_HI256_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != > XSAVE_HI16_ZMM_OFFSET); > > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != > XSAVE_PKRU_OFFSET); > > My only quibble is that these offsets are otherwise unused. This just > becomes validation > of compiler layout. > > I presume that XSAVE_BNDREG_OFFSET is not merely > ROUND_UP(offsetof(avx_state) + > sizeof(avx_state), some_pow2)? > > Do these offsets need to be migrated? Otherwise, how can one start a vm > with kvm and then > migrate to tcg? I presume the offsets above are constant for a given cpu, > and that > whatever cpu provides different offsets is not supported by tcg? Given > the lack of avx, > that's trivial these days... > > > r~ > > --0000000000004940f005c682f785 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Migration from KVM to TCG is broken anyway. The changing = offsets do break migration of a KVM guest from Intel to AMD or vice versa, = because of the difference in CPUID. That however is not changed by this pat= ch.

Paolo

Il mer 7 lug 20= 21, 03:09 Richard Henderson <richard.henderson@linaro.org> ha scritto:
On 7/5/21 3:46 AM, David Edmondson wrote:
> Given that TCG is now the only consumer of X86XSaveArea, move the
> structure definition and associated offset declarations and checks to = a
> TCG specific header.
>
> Signed-off-by: David Edmondson <david.edmondson@oracle.com<= /a>>
> ---
>=C2=A0 =C2=A0target/i386/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= | 57 ------------------------------------
>=C2=A0 =C2=A0target/i386/tcg/fpu_helper.c |=C2=A0 1 +
>=C2=A0 =C2=A0target/i386/tcg/tcg-cpu.h=C2=A0 =C2=A0 | 57 ++++++++++++++= ++++++++++++++++++++++
>=C2=A0 =C2=A03 files changed, 58 insertions(+), 57 deletions(-)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 96b672f8bd..0f7ddbfeae 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1305,48 +1305,6 @@ typedef struct XSavePKRU {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t padding;
>=C2=A0 =C2=A0} XSavePKRU;
>=C2=A0 =C2=A0
> -#define XSAVE_FCW_FSW_OFFSET=C2=A0 =C2=A0 0x000
> -#define XSAVE_FTW_FOP_OFFSET=C2=A0 =C2=A0 0x004
> -#define XSAVE_CWD_RIP_OFFSET=C2=A0 =C2=A0 0x008
> -#define XSAVE_CWD_RDP_OFFSET=C2=A0 =C2=A0 0x010
> -#define XSAVE_MXCSR_OFFSET=C2=A0 =C2=A0 =C2=A0 0x018
> -#define XSAVE_ST_SPACE_OFFSET=C2=A0 =C2=A00x020
> -#define XSAVE_XMM_SPACE_OFFSET=C2=A0 0x0a0
> -#define XSAVE_XSTATE_BV_OFFSET=C2=A0 0x200
> -#define XSAVE_AVX_OFFSET=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x240
> -#define XSAVE_BNDREG_OFFSET=C2=A0 =C2=A0 =C2=A00x3c0
> -#define XSAVE_BNDCSR_OFFSET=C2=A0 =C2=A0 =C2=A00x400
> -#define XSAVE_OPMASK_OFFSET=C2=A0 =C2=A0 =C2=A00x440
> -#define XSAVE_ZMM_HI256_OFFSET=C2=A0 0x480
> -#define XSAVE_HI16_ZMM_OFFSET=C2=A0 =C2=A00x680
> -#define XSAVE_PKRU_OFFSET=C2=A0 =C2=A0 =C2=A0 =C2=A00xa80
> -
> -typedef struct X86XSaveArea {
> -=C2=A0 =C2=A0 X86LegacyXSaveArea legacy;
> -=C2=A0 =C2=A0 X86XSaveHeader header;
> -
> -=C2=A0 =C2=A0 /* Extended save areas: */
> -
> -=C2=A0 =C2=A0 /* AVX State: */
> -=C2=A0 =C2=A0 XSaveAVX avx_state;
> -
> -=C2=A0 =C2=A0 /* Ensure that XSaveBNDREG is properly aligned. */
> -=C2=A0 =C2=A0 uint8_t padding[XSAVE_BNDREG_OFFSET
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= - sizeof(X86LegacyXSaveArea)
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= - sizeof(X86XSaveHeader)
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= - sizeof(XSaveAVX)];
> -
> -=C2=A0 =C2=A0 /* MPX State: */
> -=C2=A0 =C2=A0 XSaveBNDREG bndreg_state;
> -=C2=A0 =C2=A0 XSaveBNDCSR bndcsr_state;
> -=C2=A0 =C2=A0 /* AVX-512 State: */
> -=C2=A0 =C2=A0 XSaveOpmask opmask_state;
> -=C2=A0 =C2=A0 XSaveZMM_Hi256 zmm_hi256_state;
> -=C2=A0 =C2=A0 XSaveHi16_ZMM hi16_zmm_state;
> -=C2=A0 =C2=A0 /* PKRU State: */
> -=C2=A0 =C2=A0 XSavePKRU pkru_state;
> -} X86XSaveArea;
> -
>=C2=A0 =C2=A0QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100);
>=C2=A0 =C2=A0QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40);
>=C2=A0 =C2=A0QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40);
> @@ -1355,21 +1313,6 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) !=3D 0= x200);
>=C2=A0 =C2=A0QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400);
>=C2=A0 =C2=A0QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8);
>=C2=A0 =C2=A0
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fcw) !=3D XSAVE_FCW_F= SW_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.ftw) !=3D XSAVE_FTW_F= OP_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpip) !=3D XSAVE_CWD_= RIP_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpdp) !=3D XSAVE_CWD_= RDP_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.mxcsr) !=3D XSAVE_MXC= SR_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpregs) !=3D XSAVE_ST= _SPACE_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.xmm_regs) !=3D XSAVE_= XMM_SPACE_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) !=3D XSAVE_AVX_OF= FSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) !=3D XSAVE_BND= REG_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) !=3D XSAVE_BND= CSR_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) !=3D XSAVE_OPM= ASK_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) !=3D XSAVE_= ZMM_HI256_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) !=3D XSAVE_H= I16_ZMM_OFFSET);
> -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=3D XSAVE_PKRU_= OFFSET);
> -
>=C2=A0 =C2=A0typedef struct ExtSaveArea {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t feature, bits;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t offset, size;
> diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper= .c
> index 4e11965067..74bbe94b80 100644
> --- a/target/i386/tcg/fpu_helper.c
> +++ b/target/i386/tcg/fpu_helper.c
> @@ -20,6 +20,7 @@
>=C2=A0 =C2=A0#include "qemu/osdep.h"
>=C2=A0 =C2=A0#include <math.h>
>=C2=A0 =C2=A0#include "cpu.h"
> +#include "tcg-cpu.h"
>=C2=A0 =C2=A0#include "exec/helper-proto.h"
>=C2=A0 =C2=A0#include "fpu/softfloat.h"
>=C2=A0 =C2=A0#include "fpu/softfloat-macros.h"
> diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h
> index 36bd300af0..53a8494455 100644
> --- a/target/i386/tcg/tcg-cpu.h
> +++ b/target/i386/tcg/tcg-cpu.h
> @@ -19,6 +19,63 @@
>=C2=A0 =C2=A0#ifndef TCG_CPU_H
>=C2=A0 =C2=A0#define TCG_CPU_H
>=C2=A0 =C2=A0
> +#define XSAVE_FCW_FSW_OFFSET=C2=A0 =C2=A0 0x000
> +#define XSAVE_FTW_FOP_OFFSET=C2=A0 =C2=A0 0x004
> +#define XSAVE_CWD_RIP_OFFSET=C2=A0 =C2=A0 0x008
> +#define XSAVE_CWD_RDP_OFFSET=C2=A0 =C2=A0 0x010
> +#define XSAVE_MXCSR_OFFSET=C2=A0 =C2=A0 =C2=A0 0x018
> +#define XSAVE_ST_SPACE_OFFSET=C2=A0 =C2=A00x020
> +#define XSAVE_XMM_SPACE_OFFSET=C2=A0 0x0a0
> +#define XSAVE_XSTATE_BV_OFFSET=C2=A0 0x200
> +#define XSAVE_AVX_OFFSET=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x240
> +#define XSAVE_BNDREG_OFFSET=C2=A0 =C2=A0 =C2=A00x3c0
> +#define XSAVE_BNDCSR_OFFSET=C2=A0 =C2=A0 =C2=A00x400
> +#define XSAVE_OPMASK_OFFSET=C2=A0 =C2=A0 =C2=A00x440
> +#define XSAVE_ZMM_HI256_OFFSET=C2=A0 0x480
> +#define XSAVE_HI16_ZMM_OFFSET=C2=A0 =C2=A00x680
> +#define XSAVE_PKRU_OFFSET=C2=A0 =C2=A0 =C2=A0 =C2=A00xa80
> +
> +typedef struct X86XSaveArea {
> +=C2=A0 =C2=A0 X86LegacyXSaveArea legacy;
> +=C2=A0 =C2=A0 X86XSaveHeader header;
> +
> +=C2=A0 =C2=A0 /* Extended save areas: */
> +
> +=C2=A0 =C2=A0 /* AVX State: */
> +=C2=A0 =C2=A0 XSaveAVX avx_state;
> +
> +=C2=A0 =C2=A0 /* Ensure that XSaveBNDREG is properly aligned. */
> +=C2=A0 =C2=A0 uint8_t padding[XSAVE_BNDREG_OFFSET
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= - sizeof(X86LegacyXSaveArea)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= - sizeof(X86XSaveHeader)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= - sizeof(XSaveAVX)];
> +
> +=C2=A0 =C2=A0 /* MPX State: */
> +=C2=A0 =C2=A0 XSaveBNDREG bndreg_state;
> +=C2=A0 =C2=A0 XSaveBNDCSR bndcsr_state;
> +=C2=A0 =C2=A0 /* AVX-512 State: */
> +=C2=A0 =C2=A0 XSaveOpmask opmask_state;
> +=C2=A0 =C2=A0 XSaveZMM_Hi256 zmm_hi256_state;
> +=C2=A0 =C2=A0 XSaveHi16_ZMM hi16_zmm_state;
> +=C2=A0 =C2=A0 /* PKRU State: */
> +=C2=A0 =C2=A0 XSavePKRU pkru_state;
> +} X86XSaveArea;
> +
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fcw) !=3D XSAVE_FCW_F= SW_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.ftw) !=3D XSAVE_FTW_F= OP_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpip) !=3D XSAVE_CWD_= RIP_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpdp) !=3D XSAVE_CWD_= RDP_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.mxcsr) !=3D XSAVE_MXC= SR_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpregs) !=3D XSAVE_ST= _SPACE_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.xmm_regs) !=3D XSAVE_= XMM_SPACE_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) !=3D XSAVE_AVX_OF= FSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) !=3D XSAVE_BND= REG_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) !=3D XSAVE_BND= CSR_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) !=3D XSAVE_OPM= ASK_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) !=3D XSAVE_= ZMM_HI256_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) !=3D XSAVE_H= I16_ZMM_OFFSET);
> +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=3D XSAVE_PKRU_= OFFSET);

My only quibble is that these offsets are otherwise unused.=C2=A0 This just= becomes validation
of compiler layout.

I presume that XSAVE_BNDREG_OFFSET is not merely ROUND_UP(offsetof(avx_stat= e) +
sizeof(avx_state), some_pow2)?

Do these offsets need to be migrated?=C2=A0 Otherwise, how can one start a = vm with kvm and then
migrate to tcg?=C2=A0 I presume the offsets above are constant for a given = cpu, and that
whatever cpu provides different offsets is not supported by tcg?=C2=A0 Give= n the lack of avx,
that's trivial these days...


r~

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