From: Paolo Bonzini <pbonzini@redhat.com>
To: Atish Patra <atishp@atishpatra.org>
Cc: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-devel <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
LIU Zhiwei <lzw194868@alibaba-inc.com>
Subject: Re: [RESEND] qemu/timer: Add host ticks function for RISC-V
Date: Sat, 9 Sep 2023 09:18:02 +0200 [thread overview]
Message-ID: <CABgObfa9EehjW=p3mA-qiC8_tmkoYCT4SwF5Vtf+710OvSEw3g@mail.gmail.com> (raw)
In-Reply-To: <CAOnJCUJexy3PhmGnGNgOk3a5LWLw6ZvFkwYRXTCErGnhn_A9uA@mail.gmail.com>
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Il sab 9 set 2023, 03:35 Atish Patra <atishp@atishpatra.org> ha scritto:
> On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini <pbonzini@redhat.com> wrote:
> >
> > Queued, thanks.
> >
>
> I didn't realize it was already queued. Gmail threads failed me this time.
> @Paolo Bonzini : Can you please drop this one as this will break as
> soon as the host riscv system
> has the latest kernel ? I have provided more details in the original
> thread.
>
> https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg01941.html
If you have dynamic clock adjustment, does rdcycle increase with a fixed
frequency or does it provide the raw number of clock cycles? If the latter,
I agree that it should be provided by perf; but if the frequency is fixed
then it would be the same as rdtsc on Intel.
Paolo
>
> > Paolo
> >
> >
>
>
> --
> Regards,
> Atish
>
>
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next prev parent reply other threads:[~2023-09-09 7:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230908033129.694-1-zhiwei._5Fliu@linux.alibaba.com>
2023-09-08 10:29 ` [RESEND] qemu/timer: Add host ticks function for RISC-V Paolo Bonzini
2023-09-09 1:35 ` Atish Patra
2023-09-09 7:18 ` Paolo Bonzini [this message]
2023-09-09 14:45 ` Palmer Dabbelt
2023-09-11 5:56 ` LIU Zhiwei
2023-09-08 3:31 LIU Zhiwei
2023-09-08 22:32 ` Atish Patra
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