From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:54824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCWdO-0006eu-1L for qemu-devel@nongnu.org; Tue, 27 Mar 2012 09:40:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SCWdE-0005ED-34 for qemu-devel@nongnu.org; Tue, 27 Mar 2012 09:40:25 -0400 Received: from mail-lpp01m010-f45.google.com ([209.85.215.45]:48369) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCWdD-0005Ds-Oz for qemu-devel@nongnu.org; Tue, 27 Mar 2012 09:40:16 -0400 Received: by lahe6 with SMTP id e6so4880474lah.4 for ; Tue, 27 Mar 2012 06:40:12 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <201203261405.13760.paul@codesourcery.com> Date: Tue, 27 Mar 2012 15:40:12 +0200 Message-ID: From: Laurent Desnogues Content-Type: text/plain; charset=ISO-8859-1 Subject: Re: [Qemu-devel] [PATCH v2 0/6] ARM: AREG0 conversion List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Peter Maydell , Paul Brook , qemu-devel On Mon, Mar 26, 2012 at 7:02 PM, Blue Swirl wrote: [...] > At least stack protector is protecting more code than before (for > example TLB miss handler), but could overhead from that amount to 5%? > > Otherwise there should be just a few extra register moves here and > there, that should be cheap on modern processors. The extra moves might be cheap but their cost is obviously not 0: on top of using extra CPU core resources, code size is increased which results in more instruction cache misses. I didn't like the idea when we discussed it back in May, now it looks like we have concrete evidence the speed impact is measurable (though I'd like some more numbers than the rough 5% estimate I gave). Laurent