From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34320) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YPndH-00053R-KN for qemu-devel@nongnu.org; Mon, 23 Feb 2015 02:40:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YPndG-0006xi-HO for qemu-devel@nongnu.org; Mon, 23 Feb 2015 02:40:47 -0500 Received: from mail-ob0-x233.google.com ([2607:f8b0:4003:c01::233]:63750) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YPndG-0006xZ-Ba for qemu-devel@nongnu.org; Mon, 23 Feb 2015 02:40:46 -0500 Received: by mail-ob0-f179.google.com with SMTP id wp4so34840957obc.10 for ; Sun, 22 Feb 2015 23:40:45 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1424459998-20658-1-git-send-email-rth@twiddle.net> References: <1424459998-20658-1-git-send-email-rth@twiddle.net> Date: Mon, 23 Feb 2015 08:40:45 +0100 Message-ID: From: Laurent Desnogues Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH] tcg: Complete handling of ALWAYS and NEVER List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: "qemu-devel@nongnu.org" Hi Richard, On Fri, Feb 20, 2015 at 8:19 PM, Richard Henderson wrote: > Missing from movcond, and brcondi_i32 (but not brcondi_i64). > > Signed-off-by: Richard Henderson Tested-by: Laurent Desnogues > --- > tcg/tcg-op.c | 22 +++++++++++++++++----- > 1 file changed, 17 insertions(+), 5 deletions(-) > --- > > On 02/20/2015 05:05 AM, Laurent Desnogues wrote:> Hi Richard, >> >> this patch results in movcond with always as a condition to be >> generated for csel al. The issue is that optimize.c did not get >> patched to accept that which results in some tcg_abort to fire (in >> do_constant_folding_cond_64 in this case). > > Consider this patch to precede 08/11. Works fine. Thanks, Laurent > > r~ > --- > > diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c > index 6674bb4..f7a2767 100644 > --- a/tcg/tcg-op.c > +++ b/tcg/tcg-op.c > @@ -286,9 +286,13 @@ void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l) > > void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l) > { > - TCGv_i32 t0 = tcg_const_i32(arg2); > - tcg_gen_brcond_i32(cond, arg1, t0, l); > - tcg_temp_free_i32(t0); > + if (cond == TCG_COND_ALWAYS) { > + tcg_gen_br(l); > + } else if (cond != TCG_COND_NEVER) { > + TCGv_i32 t0 = tcg_const_i32(arg2); > + tcg_gen_brcond_i32(cond, arg1, t0, l); > + tcg_temp_free_i32(t0); > + } > } > > void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, > @@ -546,7 +550,11 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, > void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, > TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) > { > - if (TCG_TARGET_HAS_movcond_i32) { > + if (cond == TCG_COND_ALWAYS) { > + tcg_gen_mov_i32(ret, v1); > + } else if (cond == TCG_COND_NEVER) { > + tcg_gen_mov_i32(ret, v2); > + } else if (TCG_TARGET_HAS_movcond_i32) { > tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond); > } else { > TCGv_i32 t0 = tcg_temp_new_i32(); > @@ -1590,7 +1598,11 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, > void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, > TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) > { > - if (TCG_TARGET_REG_BITS == 32) { > + if (cond == TCG_COND_ALWAYS) { > + tcg_gen_mov_i64(ret, v1); > + } else if (cond == TCG_COND_NEVER) { > + tcg_gen_mov_i64(ret, v2); > + } else if (TCG_TARGET_REG_BITS == 32) { > TCGv_i32 t0 = tcg_temp_new_i32(); > TCGv_i32 t1 = tcg_temp_new_i32(); > tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, > -- > 2.1.0 >