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From: Laurent Desnogues <laurent.desnogues@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	Patch Tracking <patches@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 4/7] target/arm/translate-a64: Don't underdecode SIMD ld/st single
Date: Mon, 28 Jan 2019 12:13:31 +0100	[thread overview]
Message-ID: <CABoDooMXYPCgXbwPRVtpbtEpdeewiRx8dStCaheFMf5rwJQ2pw@mail.gmail.com> (raw)
In-Reply-To: <20190125182626.9221-5-peter.maydell@linaro.org>

On Fri, Jan 25, 2019 at 7:26 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> In the AdvSIMD load/store single structure encodings, the
> non-post-indexed case should have zeroes in [20:16] (which is the
> Rm field for the post-indexed case). Bit 31 must also be zero
> (a check we got right in ldst_multiple but not here). Correctly
> UNDEF these unallocated encodings.
>
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Thanks,

Laurent

> ---
>  target/arm/translate-a64.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index c1f0cad7691..2cade64ed25 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -3409,6 +3409,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
>  {
>      int rt = extract32(insn, 0, 5);
>      int rn = extract32(insn, 5, 5);
> +    int rm = extract32(insn, 16, 5);
>      int size = extract32(insn, 10, 2);
>      int S = extract32(insn, 12, 1);
>      int opc = extract32(insn, 13, 3);
> @@ -3424,6 +3425,15 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
>      int ebytes, xs;
>      TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
>
> +    if (extract32(insn, 31, 1)) {
> +        unallocated_encoding(s);
> +        return;
> +    }
> +    if (!is_postidx && rm != 0) {
> +        unallocated_encoding(s);
> +        return;
> +    }
> +
>      switch (scale) {
>      case 3:
>          if (!is_load || S) {
> @@ -3501,7 +3511,6 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
>      }
>
>      if (is_postidx) {
> -        int rm = extract32(insn, 16, 5);
>          if (rm == 31) {
>              tcg_gen_mov_i64(tcg_rn, tcg_addr);
>          } else {
> --
> 2.20.1
>

  reply	other threads:[~2019-01-28 11:13 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-25 18:26 [Qemu-devel] [PATCH 0/7] target/arm: Fix various underdecodings Peter Maydell
2019-01-25 18:26 ` [Qemu-devel] [PATCH 1/7] target/arm/translate-a64: Don't underdecode system instructions Peter Maydell
2019-01-28 11:09   ` Laurent Desnogues
2019-01-25 18:26 ` [Qemu-devel] [PATCH 2/7] target/arm/translate-a64: Don't underdecode PRFM Peter Maydell
2019-01-28 11:10   ` Laurent Desnogues
2019-01-25 18:26 ` [Qemu-devel] [PATCH 3/7] target/arm/translate-a64: Don't underdecode SIMD ld/st multiple Peter Maydell
2019-01-28 11:11   ` Laurent Desnogues
2019-01-25 18:26 ` [Qemu-devel] [PATCH 4/7] target/arm/translate-a64: Don't underdecode SIMD ld/st single Peter Maydell
2019-01-28 11:13   ` Laurent Desnogues [this message]
2019-01-25 18:26 ` [Qemu-devel] [PATCH 5/7] target/arm/translate-a64: Don't underdecode add/sub extended register Peter Maydell
2019-01-28 11:16   ` Laurent Desnogues
2019-01-28 11:17     ` Peter Maydell
2019-01-25 18:26 ` [Qemu-devel] [PATCH 6/7] target/arm/translate-a64: Don't underdecode FP insns Peter Maydell
2019-01-28 11:19   ` Laurent Desnogues
2019-01-25 18:26 ` [Qemu-devel] [PATCH 7/7] target/arm/translate-a64: Don't underdecode SDOT and UDOT Peter Maydell
2019-01-28 11:20   ` Laurent Desnogues

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