From: Laurent Desnogues <laurent.desnogues@gmail.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"QEMU Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support
Date: Wed, 7 Feb 2018 12:57:25 +0100 [thread overview]
Message-ID: <CABoDooMmKtM5Kwr2Vwp9=jPLBHkYUFDGfdee6TFn8uC-NetLFA@mail.gmail.com> (raw)
In-Reply-To: <CAKv+Gu8Gh-unEST2RB5bchq5jX9OSV=z=CAGGzBWWdAQYuAySQ@mail.gmail.com>
On Wed, Feb 7, 2018 at 12:53 PM, Ard Biesheuvel
<ard.biesheuvel@linaro.org> wrote:
> On 7 February 2018 at 11:49, Alex Bennée <alex.bennee@linaro.org> wrote:
>>
>> Ard Biesheuvel <ard.biesheuvel@linaro.org> writes:
>>
>>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to
>>> AArch64 user mode emulation.
>>
>> Are you aware of any processors with ARMv8.2 available yet? It might be
>> nice to have a more recent model for system emulation and the pieces
>> seems to be coming together.
>>
>
> I think Peter's idea was to have so kind of 'max' cpu type that
> enables all optional extensions in system emulation mode.
> AFAIK none of the Cortex-Axx cores that are public are available with
> these crypto features.
Cortex-A75 is ARMv8.2. It should be available in devices this year.
HTH,
Laurent
next prev parent reply other threads:[~2018-02-07 11:57 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-07 11:17 [Qemu-devel] [PATCH v6 0/5] target-arm: add SHA-3, SM3 and SHA512 instruction support Ard Biesheuvel
2018-02-07 11:17 ` [Qemu-devel] [PATCH v6 1/5] target/arm: implement SHA-512 instructions Ard Biesheuvel
2018-02-07 11:17 ` [Qemu-devel] [PATCH v6 2/5] target/arm: implement SHA-3 instructions Ard Biesheuvel
2018-02-07 11:17 ` [Qemu-devel] [PATCH v6 3/5] target/arm: implement SM3 instructions Ard Biesheuvel
2018-02-07 11:17 ` [Qemu-devel] [PATCH v6 4/5] target/arm: implement SM4 instructions Ard Biesheuvel
2018-02-07 11:17 ` [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support Ard Biesheuvel
2018-02-07 11:49 ` Alex Bennée
2018-02-07 11:53 ` Ard Biesheuvel
2018-02-07 11:57 ` Laurent Desnogues [this message]
2018-02-07 12:00 ` Ard Biesheuvel
2018-02-07 14:57 ` Alex Bennée
2018-02-07 15:07 ` Peter Maydell
2018-02-07 15:17 ` Alex Bennée
2018-02-08 12:00 ` [Qemu-devel] [PATCH v6 0/5] target-arm: add SHA-3, SM3 and SHA512 " Peter Maydell
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