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From: Laurent Desnogues <laurent.desnogues@gmail.com>
Date: Wed, 7 Feb 2018 12:57:25 +0100
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Subject: Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3,
 SM3, SM4 and SHA-512 instruction support
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To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, Peter Maydell <peter.maydell@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>

On Wed, Feb 7, 2018 at 12:53 PM, Ard Biesheuvel
<ard.biesheuvel@linaro.org> wrote:
> On 7 February 2018 at 11:49, Alex Benn=C3=A9e <alex.bennee@linaro.org> wr=
ote:
>>
>> Ard Biesheuvel <ard.biesheuvel@linaro.org> writes:
>>
>>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instruction=
s to
>>> AArch64 user mode emulation.
>>
>> Are you aware of any processors with ARMv8.2 available yet? It might be
>> nice to have a more recent model for system emulation and the pieces
>> seems to be coming together.
>>
>
> I think Peter's idea was to have so kind of 'max' cpu type that
> enables all optional extensions in system emulation mode.
> AFAIK none of the Cortex-Axx cores that are public are available with
> these crypto features.

Cortex-A75 is ARMv8.2.  It should be available in devices this year.

HTH,

Laurent