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From: Laurent Desnogues <laurent.desnogues@gmail.com>
Date: Fri, 30 Nov 2018 08:15:56 +0100
Message-ID: <CABoDooOcT-Yp__TJMj4roHMeq_T20=14-kf4L1gGNemv-gRoZg@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH 00/12] tcg: Improve register allocation for
 calls
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To: "Emilio G. Cota" <cota@braap.org>
Cc: Richard Henderson <richard.henderson@linaro.org>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>

On Fri, Nov 30, 2018 at 4:00 AM Emilio G. Cota <cota@braap.org> wrote:
>
> On Thu, Nov 29, 2018 at 19:39:15 -0500, Emilio G. Cota wrote:
> > A64 and POWER9 host numbers:
> >
> >   https://imgur.com/a/m6Pss99
> >
> > There's quite a bit of noise in the P9 measurements, but it's
> > a shared machine so I can't do much about that.
> >
> > I'll update the A64 results with error bars later tonight,
> > when I get further results.
>
> Here they are:
>
>   https://imgur.com/a/EAAapSW

What is a X-Gene A57? It's either X-Gene or A57 :-)

Thanks,

Laurent

> The second image is the same results, but zoomed in. I could
> bring the confidence intervals down by running this many times,
> but each run takes 2h and I only have access to the
> machine for a few hours at a time.
>
> Those confidence intervals are generated from only 2 runs per benchmark,
> which explains why they're so large.
>
>                 E.
>