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Date: Wed, 6 Apr 2016 14:02:25 +0200
Message-ID: <CABoDooP7gKFsUSnNiJyzt8210k8LS033QtceY0mgJtYWfrKX0A@mail.gmail.com>
From: Laurent Desnogues <laurent.desnogues@gmail.com>
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Subject: Re: [Qemu-devel] [PATCH 02/10] compiler.h: add QEMU_CACHELINE +
 QEMU_ALIGN() + QEMU_CACHELINE_ALIGNED
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To: Paolo Bonzini <pbonzini@redhat.com>
Cc: MTTCG Devel <mttcg@greensocs.com>, Peter Maydell <peter.maydell@linaro.org>, Peter Crosthwaite <crosthwaite.peter@gmail.com>, QEMU Developers <qemu-devel@nongnu.org>, "Emilio G. Cota" <cota@braap.org>, Sergey Fedorov <serge.fdrv@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, Richard Henderson <rth@twiddle.net>

On Wed, Apr 6, 2016 at 1:44 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
>
> On 05/04/2016 22:09, Llu=C3=ADs Vilanova wrote:
>> Ah. That's just an example. For cross-compilation you would use a differ=
ent
>> march argument (or none to use the default target sub-arch) and get the
>> parameter for the target processor. This should already be known by conf=
igure as
>> part of the arguments to select the cross-compiler and target architectu=
re
>> (e.g., CC).
>
> I would just use 64, with special cases for PPC and s390... even for
> AArch64 128 seems a little wasteful.

As far as I know, the only AArch64 CPU to have 128-byte cache line is
Cavium ThunderX (it seems to also be the case for Cavium MIPS-based
CPU).


Laurent