From: Laurent Desnogues <laurent.desnogues@gmail.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
Peter Maydell <peter.maydell@linaro.org>
Subject: [Qemu-devel] Aarch64 MLS bug
Date: Mon, 24 Mar 2014 10:56:36 +0100 [thread overview]
Message-ID: <CABoDooPF-WDS9z653pfA+eCPsDYztQpypyo6Mn_0jB3pySOEUg@mail.gmail.com> (raw)
Hello,
the code that implements Aarch64 AdvSIMD MLS instruction looks like this:
if (opcode == 0xf || opcode == 0x12) {
/* SABA, UABA, MLA, MLS: accumulating ops */
static NeonGenTwoOpFn * const fns[3][2] = {
{ gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
{ gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
{ tcg_gen_add_i32, tcg_gen_sub_i32 },
};
bool is_sub = (opcode == 0x12 && u); /* MLS */
genfn = fns[size][is_sub];
read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
genfn(tcg_res, tcg_res, tcg_op1);
}
The genfn call has tcg_op1 and the second tcg_res swapped.
Thanks,
Laurent
reply other threads:[~2014-03-24 9:56 UTC|newest]
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