From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E135FC433FE for ; Tue, 15 Nov 2022 00:28:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ouii5-0001lZ-G3; Mon, 14 Nov 2022 18:17:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ouieP-0003Lu-1r; Mon, 14 Nov 2022 18:14:01 -0500 Received: from mail-vs1-xe29.google.com ([2607:f8b0:4864:20::e29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ouf2Y-0006zE-Dd; Mon, 14 Nov 2022 14:22:44 -0500 Received: by mail-vs1-xe29.google.com with SMTP id i2so8061252vsc.1; Mon, 14 Nov 2022 11:22:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=dEQhebuTndEE7Cg0DMsZsBTNOVRFeHqEvwguQLO1hH0=; b=cDPIzlCy80ojTjij/kbVPfM6wsfK7LzNryjZHuPIth0aaERd6+wALQQugAhmgcqSoT dPfTdy4u29Yo3iUMaW3TfQy13FtJdyT4TFzUUMYJkdQCNvdkfGWvnfKhxVi6hZK3Xh7C 8nOktiqwSuIXWiqHi46YTEVzP6RiWXTob841om6F+f/OvHMQC0BpT4m6bouOvfWfOS+I RXqySzj4jzH9uRv94+D/w2FeZg3pOvMb66qGs7YVt6UntGOvY+JCNYVl3nc7Mz3/bse/ NX0eELOPy/vId5Qscddkj5XbeM8D61H0xhL2zdAdZsRW4l4POcniSCSAcQ13uTPhpGDp 2/eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=dEQhebuTndEE7Cg0DMsZsBTNOVRFeHqEvwguQLO1hH0=; b=dikCGIlx8j+gjcMzqLezAZdx4YXwJJb2W3A0lB/0+spt/Af2TA9LeagoOAWYkT06Xv XM9JGpsBCIDbCkghXW0U4xFx/bHQ6lJsLJQl9EtMwTb/15CrNnfNC7ZcUXUIRKMBhqRM q+DTpmUGueuDEsyyFNRn+j16Il/ap/Cf3O4kEmnlR9XOKkLXwy2LJgoZ/5rF/K/5vBmE lttT07pDzHEKfW3R56bgf8c68VLJkXrtI7DiLxmZOhWYQWXfypCN4lMmmBmvclpaMmV8 vFnFfxMzSlXki4LWTtWOotVxre2vcgr+dSDbKiSEU/ZzJ+pfBSRkz6N5zeRF8/dNyle5 +f4Q== X-Gm-Message-State: ANoB5pkDiDROSF6NdJNpEqtktfFyKVOxFME66xIK3pS2ESrvDYRg5Vfo VoLD29HNafL2ld6lwv/sYDyX+6XyC9pBCNtW1hc= X-Google-Smtp-Source: AA0mqf55GFDDM7hGuAg1WfD5jwEMn5J1cCEbDedQSPME7BhOZtFtG1pxd7vpyCVoCTfXlDKZZqEZh96PbEnjZWA7Jzo= X-Received: by 2002:a67:ea4e:0:b0:3aa:1249:73d3 with SMTP id r14-20020a67ea4e000000b003aa124973d3mr6238224vso.5.1668453759967; Mon, 14 Nov 2022 11:22:39 -0800 (PST) MIME-Version: 1.0 References: <20221112214900.24152-1-strahinja.p.jankovic@gmail.com> In-Reply-To: From: Strahinja Jankovic Date: Mon, 14 Nov 2022 20:22:28 +0100 Message-ID: Subject: Re: [PATCH] hw/sd: Fix sun4i allwinner-sdhost for U-Boot To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Beniamino Galvani Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e29; envelope-from=strahinjapjankovic@gmail.com; helo=mail-vs1-xe29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Nov 14, 2022 at 6:36 PM Peter Maydell wrote: > > On Mon, 14 Nov 2022 at 17:29, Strahinja Jankovic > wrote: > > > > Hi, > > > > Thank you for your reply. > > > > On Mon, Nov 14, 2022 at 4:42 PM Peter Maydell wrote: > > > > > > On Sat, 12 Nov 2022 at 21:49, Strahinja Jankovic > > > wrote: > > > > > > > > Trying to run U-Boot for Cubieboard (Allwinner A10) fails because it cannot > > > > access SD card. The problem is that FIFO register in current > > > > allwinner-sdhost implementation is at the address corresponding to > > > > Allwinner H3, but not A10. > > > > Linux kernel is not affected since Linux driver uses DMA access and does > > > > not use FIFO register for reading/writing. > > > > > > > > This patch adds new class parameter `is_sun4i` and based on that > > > > parameter uses register at offset 0x100 either as FIFO register (if > > > > sun4i) or as threshold register (if not sun4i; in this case register at > > > > 0x200 is FIFO register). > > > > > > > > Tested with U-Boot and Linux kernel image built for Cubieboard and > > > > OrangePi PC. > > > > > > > > Signed-off-by: Strahinja Jankovic > > > > --- > > > > hw/sd/allwinner-sdhost.c | 67 ++++++++++++++++++++++---------- > > > > include/hw/sd/allwinner-sdhost.h | 1 + > > > > 2 files changed, 47 insertions(+), 21 deletions(-) > > > > > > > > diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c > > > > index 455d6eabf6..51e5e90830 100644 > > > > --- a/hw/sd/allwinner-sdhost.c > > > > +++ b/hw/sd/allwinner-sdhost.c > > > > @@ -65,7 +65,7 @@ enum { > > > > REG_SD_DLBA = 0x84, /* Descriptor List Base Address */ > > > > REG_SD_IDST = 0x88, /* Internal DMA Controller Status */ > > > > REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */ > > > > - REG_SD_THLDC = 0x100, /* Card Threshold Control */ > > > > + REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/ > > > > REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */ > > > > REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */ > > > > REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */ > > > > @@ -415,10 +415,29 @@ static void allwinner_sdhost_dma(AwSdHostState *s) > > > > } > > > > } > > > > > > > > +static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s) > > > > +{ > > > > + uint32_t res = 0; > > > > + > > > > + if (sdbus_data_ready(&s->sdbus)) { > > > > + sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t)); > > > > + le32_to_cpus(&res); > > > > + allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); > > > > + allwinner_sdhost_auto_stop(s); > > > > + allwinner_sdhost_update_irq(s); > > > > + } else { > > > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", > > > > + __func__); > > > > + } > > > > + > > > > + return res; > > > > +} > > > > + > > > > static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, > > > > unsigned size) > > > > { > > > > AwSdHostState *s = AW_SDHOST(opaque); > > > > + AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s); > > > > uint32_t res = 0; > > > > > > > > switch (offset) { > > > > @@ -508,8 +527,12 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, > > > > case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ > > > > res = s->dmac_irq; > > > > break; > > > > - case REG_SD_THLDC: /* Card Threshold Control */ > > > > - res = s->card_threshold; > > > > + case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */ > > > > + if (sc->is_sun4i) { > > > > + res = allwinner_sdhost_fifo_read(s); > > > > + } else { > > > > + res = s->card_threshold; > > > > + } > > > > break; > > > > case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ > > > > res = s->startbit_detect; > > > > @@ -531,16 +554,7 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, > > > > res = s->status_crc; > > > > break; > > > > case REG_SD_FIFO: /* Read/Write FIFO */ > > > > - if (sdbus_data_ready(&s->sdbus)) { > > > > - sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t)); > > > > - le32_to_cpus(&res); > > > > - allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); > > > > - allwinner_sdhost_auto_stop(s); > > > > - allwinner_sdhost_update_irq(s); > > > > - } else { > > > > - qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", > > > > - __func__); > > > > - } > > > > + res = allwinner_sdhost_fifo_read(s); > > > > > > Does the sun4i really have the FIFO at both addresses, or should > > > this one do something else for sun4i ? > > > > The sun4i sdhost actually has no registers with offset higher than > > 0x100 (offset of REG_SD_THLDC in patch), so REG_SD_DSBD, all > > REG_SD_*_CRC, REG_SD_CRC_STA and REG_SD_FIFO@0x200 should not be > > accessed from application code meant to run on sun4i. That is why I > > only changed the FIFO/THLDC (offset 0x100) register behavior, since > > that change makes U-Boot work. > > > > I could update the patch so all of these registers with offset bigger > > than 0x100 log error if sun4i is selected, so that is more clear. > > Would that be ok? > > Yes, I think that's a good idea, but let's do that change as a > separate patch, so we can keep this one as it is as the bugfix. > > For this patch, > Reviewed-by: Peter Maydell > Ok, I will start preparing that separate patch for error logging for sun4i. Since this is my first time submitting a patch, is there anything else I need to do with this one? Thanks! Best regards, Strahinja > thanks > -- PMM