Re: [Qemu-devel] [PATCH] ahci: map memory via device's address space instead of address_space_memory

[Jordan Hargrave <jharg93@gmail.com>]

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The problem is the FIS registers have stale data.

SeaBIOS initialization leaves the registers:
PORT_FIS_ADDR = 0x7fae0000
PORT_FIS_ADDR_HI = 0x0

My OS initializes DMAR page tables and then enables the IOMMU translation.
Then OS initializes AHCI driver.  Writes VIRTUAL DMA to FIS registers.
eg. FIS DMA address is 0x10000 (maps to some hardware physical address via
iommu)

The OS writes 0x00 PORT_FIS_ADDR_HI -> qemu calls map_page (0x00 << 32) |
0x7fae0000... 0x7fae0000 is stale, and is not in the IOMMU page map.
Causes a non-recoverable IOMMU fault.



On Thu, Feb 26, 2015 at 8:45 AM, Stefan Hajnoczi <stefanha@gmail.com> wrote:

> On Wed, Feb 25, 2015 at 11:13:09PM -0600, Jordan Hargrave wrote:
> > Referencing this old thread:
> > https://lists.nongnu.org/archive/html/qemu-devel/2014-07/msg00606.html
> >
> > I've run into an issue recently with testing q35 DMAR/intel iommu with
> ahci
> > driver.  My ahci driver writes the upper-32 bits (PORT_FIS_ADDR_HI) first
> > then the lower 32-bits (PORT_FIS_ADDR).
> >
> > The contents of PORT_FIS_ADDR therefore are stale when the
> PORT_FIS_ADDR_HI
> > write calls map_page().  DMAR translation fails at this point as the old
> > stale address (from SEABIOS initialization) is not in the DMAR page
> table.
>
> The AHCI device tries to map on register writes to both the base and
> upper 32-bit registers.  So it should work for a driver that writes
> PORT_FIS_ADDR_HI before PORT_FIS_ADDR.
>
> Does the iommu failure pose a problem?
>
> Stefan
>

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