From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41549) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YR61u-0005sb-6y for qemu-devel@nongnu.org; Thu, 26 Feb 2015 16:31:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YR61t-0001RE-1e for qemu-devel@nongnu.org; Thu, 26 Feb 2015 16:31:34 -0500 Received: from mail-we0-x22c.google.com ([2a00:1450:400c:c03::22c]:37314) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YR61s-0001R8-Ns for qemu-devel@nongnu.org; Thu, 26 Feb 2015 16:31:32 -0500 Received: by wesw55 with SMTP id w55so14985514wes.4 for ; Thu, 26 Feb 2015 13:31:32 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20150226144504.GA23124@stefanha-thinkpad.redhat.com> References: <20150226144504.GA23124@stefanha-thinkpad.redhat.com> Date: Thu, 26 Feb 2015 15:31:32 -0600 Message-ID: From: Jordan Hargrave Content-Type: multipart/alternative; boundary=001a11c2b050bf8cf8051004795a Subject: Re: [Qemu-devel] [PATCH] ahci: map memory via device's address space instead of address_space_memory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org --001a11c2b050bf8cf8051004795a Content-Type: text/plain; charset=UTF-8 The problem is the FIS registers have stale data. SeaBIOS initialization leaves the registers: PORT_FIS_ADDR = 0x7fae0000 PORT_FIS_ADDR_HI = 0x0 My OS initializes DMAR page tables and then enables the IOMMU translation. Then OS initializes AHCI driver. Writes VIRTUAL DMA to FIS registers. eg. FIS DMA address is 0x10000 (maps to some hardware physical address via iommu) The OS writes 0x00 PORT_FIS_ADDR_HI -> qemu calls map_page (0x00 << 32) | 0x7fae0000... 0x7fae0000 is stale, and is not in the IOMMU page map. Causes a non-recoverable IOMMU fault. On Thu, Feb 26, 2015 at 8:45 AM, Stefan Hajnoczi wrote: > On Wed, Feb 25, 2015 at 11:13:09PM -0600, Jordan Hargrave wrote: > > Referencing this old thread: > > https://lists.nongnu.org/archive/html/qemu-devel/2014-07/msg00606.html > > > > I've run into an issue recently with testing q35 DMAR/intel iommu with > ahci > > driver. My ahci driver writes the upper-32 bits (PORT_FIS_ADDR_HI) first > > then the lower 32-bits (PORT_FIS_ADDR). > > > > The contents of PORT_FIS_ADDR therefore are stale when the > PORT_FIS_ADDR_HI > > write calls map_page(). DMAR translation fails at this point as the old > > stale address (from SEABIOS initialization) is not in the DMAR page > table. > > The AHCI device tries to map on register writes to both the base and > upper 32-bit registers. So it should work for a driver that writes > PORT_FIS_ADDR_HI before PORT_FIS_ADDR. > > Does the iommu failure pose a problem? > > Stefan > --001a11c2b050bf8cf8051004795a Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
The problem is the FIS registers have stale data= .

SeaBIOS initialization leaves the registers:
P= ORT_FIS_ADDR =3D 0x7fae0000
PORT_FIS_ADDR_HI =3D 0x0

<= /div>
My OS initializes DMAR page tables and then enables the IOMMU tra= nslation.=C2=A0
Then OS initializes AHCI driver.=C2=A0 Writes VIRTUAL D= MA to FIS registers.
eg. FIS DMA address is 0x10000 (maps to some hardwa= re physical address via iommu)

The OS writes 0x00 PORT_FI= S_ADDR_HI -> qemu calls map_page (0x00 << 32) | 0x7fae0000... 0x7f= ae0000 is stale, and is not in the IOMMU page map.=C2=A0 Causes a non-recov= erable IOMMU fault.



<= div class=3D"gmail_quote">On Thu, Feb 26, 2015 at 8:45 AM, Stefan Hajnoczi = <stefanha@gmail.com> wrote:
On Wed, Feb 25, 2015 at 11:13:09= PM -0600, Jordan Hargrave wrote:
> Referencing this old thread:
> https://lists.nongnu.org/archive/html/qemu-d= evel/2014-07/msg00606.html
>
> I've run into an issue recently with testing q35 DMAR/intel iommu = with ahci
> driver.=C2=A0 My ahci driver writes the upper-32 bits (PORT_FIS_ADDR_H= I) first
> then the lower 32-bits (PORT_FIS_ADDR).
>
> The contents of PORT_FIS_ADDR therefore are stale when the PORT_FIS_AD= DR_HI
> write calls map_page().=C2=A0 DMAR translation fails at this point as = the old
> stale address (from SEABIOS initialization) is not in the DMAR page ta= ble.

The AHCI device tries to map on register writes to both the bas= e and
upper 32-bit registers.=C2=A0 So it should work for a driver that writes PORT_FIS_ADDR_HI before PORT_FIS_ADDR.

Does the iommu failure pose a problem?

Stefan

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