From: Jose Martins <josemartins90@gmail.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH] target/riscv: hardwire bits in hideleg and hedeleg
Date: Thu, 24 Jun 2021 14:48:05 +0100 [thread overview]
Message-ID: <CAC41xo1Fuo6NiOE0quviuFuJXT_E5PdPOYfA1s=gdHN0vWjGnA@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKMvaLn5YUPVBngDjziud-t8P717cp-LsrOBo-VG18BMiw@mail.gmail.com>
> > +static const target_ulong vs_delegable_excps = delegable_excps &
> > + ~((1ULL << (RISCV_EXCP_S_ECALL)) |
>
> > + (1ULL << (RISCV_EXCP_VS_ECALL)) |
> > + (1ULL << (RISCV_EXCP_M_ECALL)) |
>
> These two are both read only 0, shouldn't they not be included in this list?
>
> > static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
> > {
> > - env->hedeleg = val;
> > + env->hedeleg = val & vs_delegable_excps;
>
> Because we then allow a write to occur here.
Note that the list is being bitwise negated, so both of these are
actually not writable (ie read-only 0). There is still the question
regarding the VS_ECALL (exception 10) bit raised by Zhiwei, since
table 5.2 in the spec does not explicitly classify it. However, I
believe it is safe to assume that exception 10 is non-delegable.
José
next prev parent reply other threads:[~2021-06-24 13:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-22 15:59 [PATCH] target/riscv: hardwire bits in hideleg and hedeleg Jose Martins
2021-05-25 7:22 ` LIU Zhiwei
2021-05-25 17:50 ` Jose Martins
2021-05-28 1:56 ` LIU Zhiwei
2021-05-28 2:00 ` LIU Zhiwei
2021-06-10 23:12 ` Alistair Francis
2021-06-24 13:48 ` Jose Martins [this message]
2021-07-08 4:45 ` Alistair Francis
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