From: Jason Wang <jasowang@redhat.com>
To: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
Cc: Zhenzhong Duan <zhenzhong.duan@intel.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"clg@redhat.com" <clg@redhat.com>,
"eric.auger@redhat.com" <eric.auger@redhat.com>,
"mst@redhat.com" <mst@redhat.com>,
"peterx@redhat.com" <peterx@redhat.com>,
"jgg@nvidia.com" <jgg@nvidia.com>,
"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"kevin.tian@intel.com" <kevin.tian@intel.com>,
"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
"chao.p.peng@intel.com" <chao.p.peng@intel.com>,
Yi Sun <yi.y.sun@linux.intel.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Subject: Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode
Date: Mon, 9 Dec 2024 14:24:45 +0800 [thread overview]
Message-ID: <CACGkMEs0xTf+YeCWmBbyJaQSS2RzBe2pBYzrv3n_mW+6EV4few@mail.gmail.com> (raw)
In-Reply-To: <68d3a523-19c4-4296-9df8-b98b498d4c0e@eviden.com>
On Mon, Dec 9, 2024 at 2:15 PM CLEMENT MATHIEU--DRIF
<clement.mathieu--drif@eviden.com> wrote:
>
>
>
> On 09/12/2024 04:13, Jason Wang wrote:
> > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
> >
> >
> > On Wed, Dec 4, 2024 at 2:14 PM CLEMENT MATHIEU--DRIF
> > <clement.mathieu--drif@eviden.com> wrote:
> >>
> >>
> >>
> >> On 04/12/2024 04:34, Jason Wang wrote:
> >>> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
> >>>
> >>>
> >>> On Mon, Nov 11, 2024 at 4:39 PM Zhenzhong Duan <zhenzhong.duan@intel.com> wrote:
> >>>>
> >>>> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
> >>>> related to scalable mode translation, thus there are multiple combinations.
> >>>>
> >>>> This vIOMMU implementation wants to simplify it with a new property "x-flts".
> >>>> When enabled in scalable mode, first stage translation also known as scalable
> >>>> modern mode is supported. When enabled in legacy mode, throw out error.
> >>>>
> >>>> With scalable modern mode exposed to user, also accurate the pasid entry
> >>>> check in vtd_pe_type_check().
> >>>>
> >>>> Suggested-by: Jason Wang <jasowang@redhat.com>
> >>>> Signed-off-by: Yi Liu <yi.l.liu@intel.com>
> >>>> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> >>>> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> >>>> ---
> >>>> hw/i386/intel_iommu_internal.h | 2 ++
> >>>> hw/i386/intel_iommu.c | 28 +++++++++++++++++++---------
> >>>> 2 files changed, 21 insertions(+), 9 deletions(-)
> >>>>
> >>>> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> >>>> index 2c977aa7da..e8b211e8b0 100644
> >>>> --- a/hw/i386/intel_iommu_internal.h
> >>>> +++ b/hw/i386/intel_iommu_internal.h
> >>>> @@ -195,6 +195,7 @@
> >>>> #define VTD_ECAP_PASID (1ULL << 40)
> >>>> #define VTD_ECAP_SMTS (1ULL << 43)
> >>>> #define VTD_ECAP_SLTS (1ULL << 46)
> >>>> +#define VTD_ECAP_FLTS (1ULL << 47)
> >>>>
> >>>> /* CAP_REG */
> >>>> /* (offset >> 4) << 24 */
> >>>> @@ -211,6 +212,7 @@
> >>>> #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35))
> >>>> #define VTD_CAP_DRAIN_WRITE (1ULL << 54)
> >>>> #define VTD_CAP_DRAIN_READ (1ULL << 55)
> >>>> +#define VTD_CAP_FS1GP (1ULL << 56)
> >>>> #define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WRITE)
> >>>> #define VTD_CAP_CM (1ULL << 7)
> >>>> #define VTD_PASID_ID_SHIFT 20
> >>>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> >>>> index b921793c3a..a7a81aebee 100644
> >>>> --- a/hw/i386/intel_iommu.c
> >>>> +++ b/hw/i386/intel_iommu.c
> >>>> @@ -803,16 +803,18 @@ static inline bool vtd_is_fl_level_supported(IntelIOMMUState *s, uint32_t level)
> >>>> }
> >>>>
> >>>> /* Return true if check passed, otherwise false */
> >>>> -static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu,
> >>>> - VTDPASIDEntry *pe)
> >>>> +static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe)
> >>>> {
> >>>> switch (VTD_PE_GET_TYPE(pe)) {
> >>>> - case VTD_SM_PASID_ENTRY_SLT:
> >>>> - return true;
> >>>> - case VTD_SM_PASID_ENTRY_PT:
> >>>> - return x86_iommu->pt_supported;
> >>>> case VTD_SM_PASID_ENTRY_FLT:
> >>>> + return !!(s->ecap & VTD_ECAP_FLTS);
> >>>> + case VTD_SM_PASID_ENTRY_SLT:
> >>>> + return !!(s->ecap & VTD_ECAP_SLTS);
> >>>> case VTD_SM_PASID_ENTRY_NESTED:
> >>>> + /* Not support NESTED page table type yet */
> >>>> + return false;
> >>>> + case VTD_SM_PASID_ENTRY_PT:
> >>>> + return !!(s->ecap & VTD_ECAP_PT);
> >>>> default:
> >>>> /* Unknown type */
> >>>> return false;
> >>>> @@ -861,7 +863,6 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
> >>>> uint8_t pgtt;
> >>>> uint32_t index;
> >>>> dma_addr_t entry_size;
> >>>> - X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
> >>>>
> >>>> index = VTD_PASID_TABLE_INDEX(pasid);
> >>>> entry_size = VTD_PASID_ENTRY_SIZE;
> >>>> @@ -875,7 +876,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
> >>>> }
> >>>>
> >>>> /* Do translation type check */
> >>>> - if (!vtd_pe_type_check(x86_iommu, pe)) {
> >>>> + if (!vtd_pe_type_check(s, pe)) {
> >>>> return -VTD_FR_PASID_TABLE_ENTRY_INV;
> >>>> }
> >>>>
> >>>> @@ -3827,6 +3828,7 @@ static Property vtd_properties[] = {
> >>>> VTD_HOST_ADDRESS_WIDTH),
> >>>> DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
> >>>> DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
> >>>> + DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, scalable_modern, FALSE),
> >>>> DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
> >>>> DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
> >>>> DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
> >>>> @@ -4558,7 +4560,10 @@ static void vtd_cap_init(IntelIOMMUState *s)
> >>>> }
> >>>>
> >>>> /* TODO: read cap/ecap from host to decide which cap to be exposed. */
> >>>> - if (s->scalable_mode) {
> >>>> + if (s->scalable_modern) {
> >>>> + s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_FLTS;
> >>>> + s->cap |= VTD_CAP_FS1GP;
> >>>> + } else if (s->scalable_mode) {
> >>>> s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
> >>>> }
> >>>>
> >>>> @@ -4737,6 +4742,11 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
> >>>> }
> >>>> }
> >>>>
> >>>> + if (!s->scalable_mode && s->scalable_modern) {
> >>>> + error_setg(errp, "Legacy mode: not support x-flts=on");
> >>>
> >>> This seems to be wired, should we say "scalable mode is needed for
> >>> scalable modern mode"?
> >>
> >> Hi Jason,
> >>
> >> We agreed to use the following sentence: "x-flts is only available in
> >> scalable mode"
> >>
> >> Does it look goot to you?
> >
> > Better but if we add more features to the scalable modern, we need to
> > change the error message here.
>
> Hi Jason
>
> Maybe the weirdness comes from the fact that x-flts on the command line
> is mapped to scalable_modern in the code?
Yes, actually the code checks if scalable mode is enabled if scalable
modern is enabled. But this is inconsistent with the error message
(though x-flts was implied there probably).
Thanks
>
> Thanks
> >cmd
>
> >
> > Thanks
> >
> >>
> >> Thanks
> >> cmd
> >>
> >>>
> >>>> + return false;
> >>>> + }
> >>>> +
> >>>> if (!s->scalable_modern && s->aw_bits != VTD_HOST_AW_39BIT &&
> >>>> s->aw_bits != VTD_HOST_AW_48BIT) {
> >>>> error_setg(errp, "%s mode: supported values for aw-bits are: %d, %d",
> >>>> --
> >>>> 2.34.1
> >>>>
> >>>
> >>> Thanks
> >>>
> >
next prev parent reply other threads:[~2024-12-09 6:25 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-11 8:34 [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 01/20] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 02/20] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 03/20] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 04/20] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 05/20] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 06/20] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 07/20] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 08/20] intel_iommu: Check stage-1 translation result with interrupt range Zhenzhong Duan
2024-11-13 6:55 ` CLEMENT MATHIEU--DRIF
2024-11-13 8:49 ` Duan, Zhenzhong
2024-11-14 6:04 ` CLEMENT MATHIEU--DRIF
2024-12-04 2:11 ` Jason Wang
2024-11-11 8:34 ` [PATCH v5 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 11/20] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 12/20] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-12-04 3:27 ` Jason Wang
2024-11-11 8:34 ` [PATCH v5 14/20] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 15/20] tests/acpi: q35: allow DMAR acpi table changes Zhenzhong Duan
2024-11-20 6:09 ` CLEMENT MATHIEU--DRIF
2024-12-04 3:27 ` Jason Wang
2024-11-11 8:34 ` [PATCH v5 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Zhenzhong Duan
2024-12-04 3:28 ` Jason Wang
2024-11-11 8:34 ` [PATCH v5 17/20] tests/acpi: q35: Update host address width in DMAR Zhenzhong Duan
2024-11-13 7:16 ` CLEMENT MATHIEU--DRIF
2024-11-13 8:50 ` Duan, Zhenzhong
2024-11-11 8:34 ` [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode Zhenzhong Duan
2024-11-19 6:54 ` CLEMENT MATHIEU--DRIF
2024-11-19 7:28 ` Duan, Zhenzhong
2024-11-19 8:59 ` CLEMENT MATHIEU--DRIF
2024-11-19 9:25 ` Duan, Zhenzhong
2024-11-20 6:11 ` CLEMENT MATHIEU--DRIF
2024-12-04 3:34 ` Jason Wang
2024-12-04 6:14 ` CLEMENT MATHIEU--DRIF
2024-12-09 3:13 ` Jason Wang
2024-12-09 6:14 ` CLEMENT MATHIEU--DRIF
2024-12-09 6:24 ` Jason Wang [this message]
2024-12-09 6:42 ` CLEMENT MATHIEU--DRIF
2024-12-11 2:22 ` Duan, Zhenzhong
2024-12-11 3:03 ` Jason Wang
2024-12-11 6:08 ` CLEMENT MATHIEU--DRIF
2024-11-11 8:34 ` [PATCH v5 19/20] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 20/20] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-12-03 9:00 ` [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Duan, Zhenzhong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CACGkMEs0xTf+YeCWmBbyJaQSS2RzBe2pBYzrv3n_mW+6EV4few@mail.gmail.com \
--to=jasowang@redhat.com \
--cc=alex.williamson@redhat.com \
--cc=chao.p.peng@intel.com \
--cc=clement.mathieu--drif@eviden.com \
--cc=clg@redhat.com \
--cc=eduardo@habkost.net \
--cc=eric.auger@redhat.com \
--cc=jgg@nvidia.com \
--cc=joao.m.martins@oracle.com \
--cc=kevin.tian@intel.com \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=nicolinc@nvidia.com \
--cc=pbonzini@redhat.com \
--cc=peterx@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=yi.l.liu@intel.com \
--cc=yi.y.sun@linux.intel.com \
--cc=zhenzhong.duan@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).