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Sun, 08 Dec 2024 22:24:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IGU+O1/J2qRqECF7YvY+alaEETETqb9haKkNLcu/OqX4k+JFy9jjbXDvapbxdqD5afYJpedlm8iYlm7hDOoKyU= X-Received: by 2002:a17:903:18a:b0:20d:cb6:11e with SMTP id d9443c01a7336-21614d50de0mr149736975ad.26.1733725496795; Sun, 08 Dec 2024 22:24:56 -0800 (PST) MIME-Version: 1.0 References: <20241111083457.2090664-1-zhenzhong.duan@intel.com> <20241111083457.2090664-19-zhenzhong.duan@intel.com> <7126398e-fc27-4d4f-894b-f71b012f98e1@eviden.com> <68d3a523-19c4-4296-9df8-b98b498d4c0e@eviden.com> In-Reply-To: <68d3a523-19c4-4296-9df8-b98b498d4c0e@eviden.com> From: Jason Wang Date: Mon, 9 Dec 2024 14:24:45 +0800 Message-ID: Subject: Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode To: CLEMENT MATHIEU--DRIF Cc: Zhenzhong Duan , "qemu-devel@nongnu.org" , "alex.williamson@redhat.com" , "clg@redhat.com" , "eric.auger@redhat.com" , "mst@redhat.com" , "peterx@redhat.com" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "joao.m.martins@oracle.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "chao.p.peng@intel.com" , Yi Sun , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.495, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Dec 9, 2024 at 2:15=E2=80=AFPM CLEMENT MATHIEU--DRIF wrote: > > > > On 09/12/2024 04:13, Jason Wang wrote: > > Caution: External email. Do not open attachments or click links, unless= this email comes from a known sender and you know the content is safe. > > > > > > On Wed, Dec 4, 2024 at 2:14=E2=80=AFPM CLEMENT MATHIEU--DRIF > > wrote: > >> > >> > >> > >> On 04/12/2024 04:34, Jason Wang wrote: > >>> Caution: External email. Do not open attachments or click links, unle= ss this email comes from a known sender and you know the content is safe. > >>> > >>> > >>> On Mon, Nov 11, 2024 at 4:39=E2=80=AFPM Zhenzhong Duan wrote: > >>>> > >>>> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capab= ilities > >>>> related to scalable mode translation, thus there are multiple combin= ations. > >>>> > >>>> This vIOMMU implementation wants to simplify it with a new property = "x-flts". > >>>> When enabled in scalable mode, first stage translation also known as= scalable > >>>> modern mode is supported. When enabled in legacy mode, throw out err= or. > >>>> > >>>> With scalable modern mode exposed to user, also accurate the pasid e= ntry > >>>> check in vtd_pe_type_check(). > >>>> > >>>> Suggested-by: Jason Wang > >>>> Signed-off-by: Yi Liu > >>>> Signed-off-by: Yi Sun > >>>> Signed-off-by: Zhenzhong Duan > >>>> --- > >>>> hw/i386/intel_iommu_internal.h | 2 ++ > >>>> hw/i386/intel_iommu.c | 28 +++++++++++++++++++--------- > >>>> 2 files changed, 21 insertions(+), 9 deletions(-) > >>>> > >>>> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_in= ternal.h > >>>> index 2c977aa7da..e8b211e8b0 100644 > >>>> --- a/hw/i386/intel_iommu_internal.h > >>>> +++ b/hw/i386/intel_iommu_internal.h > >>>> @@ -195,6 +195,7 @@ > >>>> #define VTD_ECAP_PASID (1ULL << 40) > >>>> #define VTD_ECAP_SMTS (1ULL << 43) > >>>> #define VTD_ECAP_SLTS (1ULL << 46) > >>>> +#define VTD_ECAP_FLTS (1ULL << 47) > >>>> > >>>> /* CAP_REG */ > >>>> /* (offset >> 4) << 24 */ > >>>> @@ -211,6 +212,7 @@ > >>>> #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) > >>>> #define VTD_CAP_DRAIN_WRITE (1ULL << 54) > >>>> #define VTD_CAP_DRAIN_READ (1ULL << 55) > >>>> +#define VTD_CAP_FS1GP (1ULL << 56) > >>>> #define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP= _DRAIN_WRITE) > >>>> #define VTD_CAP_CM (1ULL << 7) > >>>> #define VTD_PASID_ID_SHIFT 20 > >>>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > >>>> index b921793c3a..a7a81aebee 100644 > >>>> --- a/hw/i386/intel_iommu.c > >>>> +++ b/hw/i386/intel_iommu.c > >>>> @@ -803,16 +803,18 @@ static inline bool vtd_is_fl_level_supported(I= ntelIOMMUState *s, uint32_t level) > >>>> } > >>>> > >>>> /* Return true if check passed, otherwise false */ > >>>> -static inline bool vtd_pe_type_check(X86IOMMUState *x86_iommu, > >>>> - VTDPASIDEntry *pe) > >>>> +static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEn= try *pe) > >>>> { > >>>> switch (VTD_PE_GET_TYPE(pe)) { > >>>> - case VTD_SM_PASID_ENTRY_SLT: > >>>> - return true; > >>>> - case VTD_SM_PASID_ENTRY_PT: > >>>> - return x86_iommu->pt_supported; > >>>> case VTD_SM_PASID_ENTRY_FLT: > >>>> + return !!(s->ecap & VTD_ECAP_FLTS); > >>>> + case VTD_SM_PASID_ENTRY_SLT: > >>>> + return !!(s->ecap & VTD_ECAP_SLTS); > >>>> case VTD_SM_PASID_ENTRY_NESTED: > >>>> + /* Not support NESTED page table type yet */ > >>>> + return false; > >>>> + case VTD_SM_PASID_ENTRY_PT: > >>>> + return !!(s->ecap & VTD_ECAP_PT); > >>>> default: > >>>> /* Unknown type */ > >>>> return false; > >>>> @@ -861,7 +863,6 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelI= OMMUState *s, > >>>> uint8_t pgtt; > >>>> uint32_t index; > >>>> dma_addr_t entry_size; > >>>> - X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); > >>>> > >>>> index =3D VTD_PASID_TABLE_INDEX(pasid); > >>>> entry_size =3D VTD_PASID_ENTRY_SIZE; > >>>> @@ -875,7 +876,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelI= OMMUState *s, > >>>> } > >>>> > >>>> /* Do translation type check */ > >>>> - if (!vtd_pe_type_check(x86_iommu, pe)) { > >>>> + if (!vtd_pe_type_check(s, pe)) { > >>>> return -VTD_FR_PASID_TABLE_ENTRY_INV; > >>>> } > >>>> > >>>> @@ -3827,6 +3828,7 @@ static Property vtd_properties[] =3D { > >>>> VTD_HOST_ADDRESS_WIDTH), > >>>> DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mod= e, FALSE), > >>>> DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable= _mode, FALSE), > >>>> + DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, scalable_modern, FA= LSE), > >>>> DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_cont= rol, false), > >>>> DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, fals= e), > >>>> DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, tru= e), > >>>> @@ -4558,7 +4560,10 @@ static void vtd_cap_init(IntelIOMMUState *s) > >>>> } > >>>> > >>>> /* TODO: read cap/ecap from host to decide which cap to be ex= posed. */ > >>>> - if (s->scalable_mode) { > >>>> + if (s->scalable_modern) { > >>>> + s->ecap |=3D VTD_ECAP_SMTS | VTD_ECAP_FLTS; > >>>> + s->cap |=3D VTD_CAP_FS1GP; > >>>> + } else if (s->scalable_mode) { > >>>> s->ecap |=3D VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS= ; > >>>> } > >>>> > >>>> @@ -4737,6 +4742,11 @@ static bool vtd_decide_config(IntelIOMMUState= *s, Error **errp) > >>>> } > >>>> } > >>>> > >>>> + if (!s->scalable_mode && s->scalable_modern) { > >>>> + error_setg(errp, "Legacy mode: not support x-flts=3Don"); > >>> > >>> This seems to be wired, should we say "scalable mode is needed for > >>> scalable modern mode"? > >> > >> Hi Jason, > >> > >> We agreed to use the following sentence: "x-flts is only available in > >> scalable mode" > >> > >> Does it look goot to you? > > > > Better but if we add more features to the scalable modern, we need to > > change the error message here. > > Hi Jason > > Maybe the weirdness comes from the fact that x-flts on the command line > is mapped to scalable_modern in the code? Yes, actually the code checks if scalable mode is enabled if scalable modern is enabled. But this is inconsistent with the error message (though x-flts was implied there probably). Thanks > > Thanks > >cmd > > > > > Thanks > > > >> > >> Thanks > >> cmd > >> > >>> > >>>> + return false; > >>>> + } > >>>> + > >>>> if (!s->scalable_modern && s->aw_bits !=3D VTD_HOST_AW_39BIT = && > >>>> s->aw_bits !=3D VTD_HOST_AW_48BIT) { > >>>> error_setg(errp, "%s mode: supported values for aw-bits a= re: %d, %d", > >>>> -- > >>>> 2.34.1 > >>>> > >>> > >>> Thanks > >>> > >