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From: Jason Wang <jasowang@redhat.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>
Cc: qemu-devel@nongnu.org, alex.williamson@redhat.com,
	clg@redhat.com,  eric.auger@redhat.com, mst@redhat.com,
	peterx@redhat.com, jgg@nvidia.com,  nicolinc@nvidia.com,
	joao.m.martins@oracle.com,  clement.mathieu--drif@eviden.com,
	kevin.tian@intel.com, yi.l.liu@intel.com,  chao.p.peng@intel.com,
	Paolo Bonzini <pbonzini@redhat.com>,
	 Richard Henderson <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>,
	 Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: Re: [PATCH v3 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation
Date: Fri, 27 Sep 2024 12:08:10 +0800	[thread overview]
Message-ID: <CACGkMEscZB9f6toOcm_+3pQknDgnp3r6MvzbejB9BVEsKz7rjA@mail.gmail.com> (raw)
In-Reply-To: <20240911052255.1294071-13-zhenzhong.duan@intel.com>

On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan <zhenzhong.duan@intel.com> wrote:
>
> From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
>
> Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
>  hw/i386/intel_iommu_internal.h | 11 ++++++++
>  hw/i386/intel_iommu.c          | 50 ++++++++++++++++++++++++++++++++++
>  2 files changed, 61 insertions(+)
>
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index 4f2c3a9350..52bdbf3bc5 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -375,6 +375,7 @@ typedef union VTDInvDesc VTDInvDesc;
>  #define VTD_INV_DESC_WAIT               0x5 /* Invalidation Wait Descriptor */
>  #define VTD_INV_DESC_PIOTLB             0x6 /* PASID-IOTLB Invalidate Desc */
>  #define VTD_INV_DESC_PC                 0x7 /* PASID-cache Invalidate Desc */
> +#define VTD_INV_DESC_DEV_PIOTLB         0x8 /* PASID-based-DIOTLB inv_desc*/
>  #define VTD_INV_DESC_NONE               0   /* Not an Invalidate Descriptor */
>
>  /* Masks for Invalidation Wait Descriptor*/
> @@ -413,6 +414,16 @@ typedef union VTDInvDesc VTDInvDesc;
>  #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL
>  #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
>
> +/* Mask for PASID Device IOTLB Invalidate Descriptor */
> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(val) ((val) & \
> +                                                   0xfffffffffffff000ULL)
> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(val) ((val >> 11) & 0x1)
> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(val) ((val) & 0x1)
> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(val) (((val) >> 16) & 0xffffULL)
> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(val) ((val >> 32) & 0xfffffULL)
> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_HI 0x7feULL
> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_LO 0xfff000000000f000ULL
> +
>  /* Rsvd field masks for spte */
>  #define VTD_SPTE_SNP 0x800ULL
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index d28c862598..4cf56924e1 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3017,6 +3017,49 @@ static void do_invalidate_device_tlb(VTDAddressSpace *vtd_dev_as,
>      memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event);
>  }
>
> +static bool vtd_process_device_piotlb_desc(IntelIOMMUState *s,
> +                                           VTDInvDesc *inv_desc)
> +{
> +    uint16_t sid;
> +    VTDAddressSpace *vtd_dev_as;
> +    bool size;
> +    bool global;
> +    hwaddr addr;
> +    uint32_t pasid;
> +
> +    if ((inv_desc->hi & VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_HI) ||
> +         (inv_desc->lo & VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_LO)) {
> +        error_report_once("%s: invalid pasid-based dev iotlb inv desc:"
> +                          "hi=%"PRIx64 "(reserved nonzero)",
> +                          __func__, inv_desc->hi);
> +        return false;
> +    }
> +
> +    global = VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(inv_desc->hi);
> +    size = VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(inv_desc->hi);
> +    addr = VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(inv_desc->hi);
> +    sid = VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(inv_desc->lo);
> +    if (global) {
> +        QLIST_FOREACH(vtd_dev_as, &s->vtd_as_with_notifiers, next) {
> +            if ((vtd_dev_as->pasid != PCI_NO_PASID) &&
> +                (PCI_BUILD_BDF(pci_bus_num(vtd_dev_as->bus),
> +                                           vtd_dev_as->devfn) == sid)) {
> +                do_invalidate_device_tlb(vtd_dev_as, size, addr);
> +            }
> +        }
> +    } else {
> +        pasid = VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(inv_desc->lo);
> +        vtd_dev_as = vtd_get_as_by_sid_and_pasid(s, sid, pasid);
> +        if (!vtd_dev_as) {
> +            return true;
> +        }
> +
> +        do_invalidate_device_tlb(vtd_dev_as, size, addr);

Question:

I wonder if current vhost (which has a device IOTLB abstraction via
virtio-pci) can work with this (PASID based IOTLB invalidation)

THanks


> +    }
> +
> +    return true;
> +}
> +
>  static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
>                                            VTDInvDesc *inv_desc)
>  {
> @@ -3111,6 +3154,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
>          }
>          break;
>
> +    case VTD_INV_DESC_DEV_PIOTLB:
> +        trace_vtd_inv_desc("device-piotlb", inv_desc.hi, inv_desc.lo);
> +        if (!vtd_process_device_piotlb_desc(s, &inv_desc)) {
> +            return false;
> +        }
> +        break;
> +
>      case VTD_INV_DESC_DEVICE:
>          trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo);
>          if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
> --
> 2.34.1
>



  reply	other threads:[~2024-09-27  4:10 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-11  5:22 [PATCH v3 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-09-11  5:22 ` [PATCH v3 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-09-27  0:12   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-09-27  0:13   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-09-11  6:26   ` CLEMENT MATHIEU--DRIF
2024-09-11  8:38     ` Duan, Zhenzhong
2024-09-27  0:15   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-09-11  6:54   ` CLEMENT MATHIEU--DRIF
2024-09-27  3:47   ` Jason Wang
2024-09-27  6:38     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-09-27  3:47   ` Jason Wang
2024-09-29 12:43   ` Yi Liu
2024-09-30  3:43     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-09-27  4:07   ` Jason Wang
2024-09-29 13:58   ` Yi Liu
2024-09-30  5:55     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-09-27  4:07   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-09-27  4:07   ` Jason Wang
2024-09-27  6:38     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-09-27  4:07   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 11/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang [this message]
2024-09-27  7:17     ` Duan, Zhenzhong
2024-09-27  8:02       ` Duan, Zhenzhong
2024-09-29  1:59       ` Jason Wang
2024-09-29  2:22         ` Duan, Zhenzhong
2024-12-16  8:21         ` Duan, Zhenzhong
2024-12-17  2:13           ` Jason Wang
2024-12-17  6:06             ` CLEMENT MATHIEU--DRIF
2024-09-11  5:22 ` [PATCH v3 13/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-09-11  5:22 ` [PATCH v3 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-27  6:38     ` Duan, Zhenzhong
2024-09-29  2:02       ` Jason Wang
2024-09-29  2:57         ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose " Zhenzhong Duan
2024-09-11  6:54   ` CLEMENT MATHIEU--DRIF
2024-09-27  4:08   ` Jason Wang
2024-09-27  6:39     ` Duan, Zhenzhong
2024-09-29  2:00       ` Jason Wang
2024-09-29  2:44         ` Duan, Zhenzhong
2024-11-04  3:24           ` Yi Liu
2024-11-04  7:13             ` CLEMENT MATHIEU--DRIF
2024-09-11  5:22 ` [PATCH v3 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-27  6:39     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-11  6:56 ` [PATCH v3 00/17] intel_iommu: Enable stage-1 translation for emulated device CLEMENT MATHIEU--DRIF
2024-09-11  8:43   ` Duan, Zhenzhong
2024-09-11 10:43     ` Michael S. Tsirkin
2024-09-26  9:25 ` Duan, Zhenzhong

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