qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Jason Wang <jasowang@redhat.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>
Cc: qemu-devel@nongnu.org, alex.williamson@redhat.com,
	clg@redhat.com,  eric.auger@redhat.com, mst@redhat.com,
	peterx@redhat.com, jgg@nvidia.com,  nicolinc@nvidia.com,
	joao.m.martins@oracle.com,  clement.mathieu--drif@eviden.com,
	kevin.tian@intel.com, yi.l.liu@intel.com,  chao.p.peng@intel.com,
	Paolo Bonzini <pbonzini@redhat.com>,
	 Richard Henderson <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>,
	 Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: Re: [PATCH v3 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting
Date: Fri, 27 Sep 2024 12:08:21 +0800	[thread overview]
Message-ID: <CACGkMEtPQGmJvYkfCfjNrsrumYKvBH8SXYdT0ZpToJ3Ac5DhYQ@mail.gmail.com> (raw)
In-Reply-To: <20240911052255.1294071-17-zhenzhong.duan@intel.com>

On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan <zhenzhong.duan@intel.com> wrote:
>
> This gives user flexibility to turn off FS1GP for debug purpose.
>
> It is also useful for future nesting feature. When host IOMMU doesn't
> support FS1GP but vIOMMU does, nested page table on host side works
> after turn FS1GP off in vIOMMU.
>
> This property has no effect when vIOMMU isn't in scalable modern
> mode.

It looks to me there's no need to have an "x" prefix for this.

Other looks good.

>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
> ---
>  include/hw/i386/intel_iommu.h | 1 +
>  hw/i386/intel_iommu.c         | 5 ++++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
> index 650641544c..f6d9b41b80 100644
> --- a/include/hw/i386/intel_iommu.h
> +++ b/include/hw/i386/intel_iommu.h
> @@ -308,6 +308,7 @@ struct IntelIOMMUState {
>      bool dma_drain;                 /* Whether DMA r/w draining enabled */
>      bool dma_translation;           /* Whether DMA translation supported */
>      bool pasid;                     /* Whether to support PASID */
> +    bool fs1gp;                     /* First Stage 1-GByte Page Support */
>
>      /*
>       * Protects IOMMU states in general.  Currently it protects the
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index bb3ed48281..8b40aace8b 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3779,6 +3779,7 @@ static Property vtd_properties[] = {
>      DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
>      DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
>      DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, true),
> +    DEFINE_PROP_BOOL("x-cap-fs1gp", IntelIOMMUState, fs1gp, true),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> @@ -4507,7 +4508,9 @@ static void vtd_cap_init(IntelIOMMUState *s)
>      /* TODO: read cap/ecap from host to decide which cap to be exposed. */
>      if (s->scalable_modern) {
>          s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_FLTS;
> -        s->cap |= VTD_CAP_FS1GP;
> +        if (s->fs1gp) {
> +            s->cap |= VTD_CAP_FS1GP;
> +        }
>      } else if (s->scalable_mode) {
>          s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
>      }
> --
> 2.34.1
>

Thanks



  reply	other threads:[~2024-09-27  4:09 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-11  5:22 [PATCH v3 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-09-11  5:22 ` [PATCH v3 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-09-27  0:12   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-09-27  0:13   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-09-11  6:26   ` CLEMENT MATHIEU--DRIF
2024-09-11  8:38     ` Duan, Zhenzhong
2024-09-27  0:15   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-09-11  6:54   ` CLEMENT MATHIEU--DRIF
2024-09-27  3:47   ` Jason Wang
2024-09-27  6:38     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-09-27  3:47   ` Jason Wang
2024-09-29 12:43   ` Yi Liu
2024-09-30  3:43     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-09-27  4:07   ` Jason Wang
2024-09-29 13:58   ` Yi Liu
2024-09-30  5:55     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-09-27  4:07   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-09-27  4:07   ` Jason Wang
2024-09-27  6:38     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-09-27  4:07   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 11/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-11  5:22 ` [PATCH v3 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-27  7:17     ` Duan, Zhenzhong
2024-09-27  8:02       ` Duan, Zhenzhong
2024-09-29  1:59       ` Jason Wang
2024-09-29  2:22         ` Duan, Zhenzhong
2024-12-16  8:21         ` Duan, Zhenzhong
2024-12-17  2:13           ` Jason Wang
2024-12-17  6:06             ` CLEMENT MATHIEU--DRIF
2024-09-11  5:22 ` [PATCH v3 13/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-09-11  5:22 ` [PATCH v3 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-27  6:38     ` Duan, Zhenzhong
2024-09-29  2:02       ` Jason Wang
2024-09-29  2:57         ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose " Zhenzhong Duan
2024-09-11  6:54   ` CLEMENT MATHIEU--DRIF
2024-09-27  4:08   ` Jason Wang
2024-09-27  6:39     ` Duan, Zhenzhong
2024-09-29  2:00       ` Jason Wang
2024-09-29  2:44         ` Duan, Zhenzhong
2024-11-04  3:24           ` Yi Liu
2024-11-04  7:13             ` CLEMENT MATHIEU--DRIF
2024-09-11  5:22 ` [PATCH v3 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang [this message]
2024-09-27  6:39     ` Duan, Zhenzhong
2024-09-11  5:22 ` [PATCH v3 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-09-27  4:08   ` Jason Wang
2024-09-11  6:56 ` [PATCH v3 00/17] intel_iommu: Enable stage-1 translation for emulated device CLEMENT MATHIEU--DRIF
2024-09-11  8:43   ` Duan, Zhenzhong
2024-09-11 10:43     ` Michael S. Tsirkin
2024-09-26  9:25 ` Duan, Zhenzhong

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CACGkMEtPQGmJvYkfCfjNrsrumYKvBH8SXYdT0ZpToJ3Ac5DhYQ@mail.gmail.com \
    --to=jasowang@redhat.com \
    --cc=alex.williamson@redhat.com \
    --cc=chao.p.peng@intel.com \
    --cc=clement.mathieu--drif@eviden.com \
    --cc=clg@redhat.com \
    --cc=eduardo@habkost.net \
    --cc=eric.auger@redhat.com \
    --cc=jgg@nvidia.com \
    --cc=joao.m.martins@oracle.com \
    --cc=kevin.tian@intel.com \
    --cc=marcel.apfelbaum@gmail.com \
    --cc=mst@redhat.com \
    --cc=nicolinc@nvidia.com \
    --cc=pbonzini@redhat.com \
    --cc=peterx@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=yi.l.liu@intel.com \
    --cc=zhenzhong.duan@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).