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Sun, 14 Dec 2025 23:33:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IF6gqEVvlkTJbxfvkQkEciUsqkV24NUoLy7KTPy6DA2wS0pvUOR4KPziVc1M4NS02+hPHZkqNRVSXyQOA2wo8c= X-Received: by 2002:a05:6102:6a94:b0:5db:d07c:21a8 with SMTP id ada2fe7eead31-5e8277d7832mr3273372137.25.1765783996388; Sun, 14 Dec 2025 23:33:16 -0800 (PST) MIME-Version: 1.0 References: <20251117093729.1121324-1-zhenzhong.duan@intel.com> <20251117093729.1121324-3-zhenzhong.duan@intel.com> <4618ef6c-9f54-45bf-a95c-5f813f9a2365@intel.com> In-Reply-To: <4618ef6c-9f54-45bf-a95c-5f813f9a2365@intel.com> From: Jason Wang Date: Mon, 15 Dec 2025 15:33:03 +0800 X-Gm-Features: AQt7F2qBkvPbDmgjrJOurzdG4H4MaY7uwkXmX-WF4yL98Gm4qt5kd7EIfqNygSk Message-ID: Subject: Re: [PATCH v8 02/23] intel_iommu: Delete RPS capability related supporting code To: Yi Liu Cc: Zhenzhong Duan , qemu-devel@nongnu.org, alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, chao.p.peng@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Dec 11, 2025 at 6:57=E2=80=AFPM Yi Liu wrote: > > On 2025/12/11 16:22, Jason Wang wrote: > > On Mon, Nov 17, 2025 at 5:38=E2=80=AFPM Zhenzhong Duan wrote: > >> > >> RID-PASID Support(RPS) is not set in vIOMMU ECAP register, the support= ing > >> code is there but never takes effect. > >> > >> Meanwhile, according to VTD spec section 3.4.3: > >> "Implementations not supporting RID_PASID capability (ECAP_REG.RPS is = 0b), > >> use a PASID value of 0 to perform address translation for requests wit= hout > >> PASID." > >> > >> We should delete the supporting code which fetches RID_PASID field fro= m > >> scalable context entry and use 0 as RID_PASID directly, because RID_PA= SID > >> field is ignored if no RPS support according to spec. > >> > >> This simplifies the code and doesn't bring any penalty. > >> > >> Suggested-by: Yi Liu > >> Signed-off-by: Zhenzhong Duan > >> --- > > > > Is the feature deprecated in the spec? If not, it should be still > > better to enable it. > > Hi Jason, > > The feature is still in the spec. However, using PASID#0 for the > requests without pasid is aligned across vendors. So the linux iommu > subsystem uses PASID#0 to differentiate the pasid path and non-pasid > path like below: > > commit bc06f7f66de404ae6323963361fe4e2f5f71a1e5 > Author: Yi Liu > Date: Fri Mar 21 10:19:26 2025 -0700 > > iommufd/device: Only add reserved_iova in non-pasid path > > As the pasid is passed through the attach/replace/detach helpers, it= is > necessary to ensure only the non-pasid path adds reserved_iova. > > Link: > https://patch.msgid.link/r/20250321171940.7213-5-yi.l.liu@intel.com > Reviewed-by: Jason Gunthorpe > Reviewed-by: Kevin Tian > Reviewed-by: Nicolin Chen > Reviewed-by: Lu Baolu > Signed-off-by: Yi Liu > Tested-by: Nicolin Chen > Signed-off-by: Jason Gunthorpe > > diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/devic= e.c > index 7051feda2fab..4625f084f7d0 100644 > --- a/drivers/iommu/iommufd/device.c > +++ b/drivers/iommu/iommufd/device.c > @@ -483,6 +483,7 @@ int iommufd_hw_pagetable_attach(struct > iommufd_hw_pagetable *hwpt, > struct iommufd_device *idev, ioasid_t > pasid) > { > struct iommufd_hwpt_paging *hwpt_paging =3D find_hwpt_paging(hwp= t); > + bool attach_resv =3D hwpt_paging && pasid =3D=3D IOMMU_NO_PASID; > int rc; > > > So even though intel hardware report RPS=3D1, the linux intel iommu > driver uses PASID#0 as rid_pasid and ignores the RPS value. Probably, but we need to support OSes other than Linux. > So > I don't think we will ever report RPS=3D1 to VM. Also, as Zhenzhong's > commit message states, current vIOMMU does not report RPS, the logic to > retrieve rid_pasid from context entry is not necessary as well. Based on > the fact, I think it is nice to drop the support. Please let us know if > you have other ideas. I'm fine to drop that, just want to double check if it's worth keeping with an option to enable it. Thanks > > Regards, > Yi Liu >