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Mon, 16 Dec 2024 18:13:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IGtqbmmSjVisTI/K/P4GN2VSEDjirNw18cpNTFsQKa1PtHtZKuAFT8wJb3gWVcQXVdMk6SOiVzxaIlHo2VCAv8= X-Received: by 2002:a17:90b:314d:b0:2ee:f80c:6884 with SMTP id 98e67ed59e1d1-2f2901b44c3mr21813755a91.33.1734401632963; Mon, 16 Dec 2024 18:13:52 -0800 (PST) MIME-Version: 1.0 References: <20240911052255.1294071-1-zhenzhong.duan@intel.com> <20240911052255.1294071-13-zhenzhong.duan@intel.com> In-Reply-To: From: Jason Wang Date: Tue, 17 Dec 2024 10:13:41 +0800 Message-ID: Subject: Re: [PATCH v3 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation To: "Duan, Zhenzhong" Cc: "qemu-devel@nongnu.org" , "alex.williamson@redhat.com" , "clg@redhat.com" , "eric.auger@redhat.com" , "mst@redhat.com" , "peterx@redhat.com" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "joao.m.martins@oracle.com" , "clement.mathieu--drif@eviden.com" , "Tian, Kevin" , "Liu, Yi L" , "Peng, Chao P" , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1.13, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Dec 16, 2024 at 4:22=E2=80=AFPM Duan, Zhenzhong wrote: > > > > >-----Original Message----- > >From: Jason Wang > >Sent: Sunday, September 29, 2024 9:59 AM > >Subject: Re: [PATCH v3 12/17] intel_iommu: Add support for PASID-based d= evice > >IOTLB invalidation > > > >On Fri, Sep 27, 2024 at 3:18=E2=80=AFPM Duan, Zhenzhong > > wrote: > >> > >> > >> > >> >-----Original Message----- > >> >From: Jason Wang > >> >Subject: Re: [PATCH v3 12/17] intel_iommu: Add support for PASID-base= d > >> >device IOTLB invalidation > >> > > >> >On Wed, Sep 11, 2024 at 1:27=E2=80=AFPM Zhenzhong Duan > >> > wrote: > >> >> > >> >> From: Cl=C3=A9ment Mathieu--Drif > >> >> > >> >> Signed-off-by: Cl=C3=A9ment Mathieu--Drif > >> >> Signed-off-by: Zhenzhong Duan > >> >> --- > >> >> hw/i386/intel_iommu_internal.h | 11 ++++++++ > >> >> hw/i386/intel_iommu.c | 50 > >> >++++++++++++++++++++++++++++++++++ > >> >> 2 files changed, 61 insertions(+) > >> >> > >> >> diff --git a/hw/i386/intel_iommu_internal.h > >> >b/hw/i386/intel_iommu_internal.h > >> >> index 4f2c3a9350..52bdbf3bc5 100644 > >> >> --- a/hw/i386/intel_iommu_internal.h > >> >> +++ b/hw/i386/intel_iommu_internal.h > >> >> @@ -375,6 +375,7 @@ typedef union VTDInvDesc VTDInvDesc; > >> >> #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait D= escriptor > >> >*/ > >> >> #define VTD_INV_DESC_PIOTLB 0x6 /* PASID-IOTLB Invalid= ate Desc > >> >*/ > >> >> #define VTD_INV_DESC_PC 0x7 /* PASID-cache Invalid= ate Desc */ > >> >> +#define VTD_INV_DESC_DEV_PIOTLB 0x8 /* PASID-based-DIOTLB > >> >inv_desc*/ > >> >> #define VTD_INV_DESC_NONE 0 /* Not an Invalidate D= escriptor > >> >*/ > >> >> > >> >> /* Masks for Invalidation Wait Descriptor*/ > >> >> @@ -413,6 +414,16 @@ typedef union VTDInvDesc VTDInvDesc; > >> >> #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL > >> >> #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 > >> >> > >> >> +/* Mask for PASID Device IOTLB Invalidate Descriptor */ > >> >> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(val) ((val) & \ > >> >> + 0xfffffffffffff= 000ULL) > >> >> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(val) ((val >> 11) & 0= x1) > >> >> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(val) ((val) & 0x1) > >> >> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(val) (((val) >> 16) & > >> >0xffffULL) > >> >> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(val) ((val >> 32) & > >> >0xfffffULL) > >> >> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_HI 0x7feULL > >> >> +#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_LO > >> >0xfff000000000f000ULL > >> >> + > >> >> /* Rsvd field masks for spte */ > >> >> #define VTD_SPTE_SNP 0x800ULL > >> >> > >> >> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > >> >> index d28c862598..4cf56924e1 100644 > >> >> --- a/hw/i386/intel_iommu.c > >> >> +++ b/hw/i386/intel_iommu.c > >> >> @@ -3017,6 +3017,49 @@ static void > >> >do_invalidate_device_tlb(VTDAddressSpace *vtd_dev_as, > >> >> memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event); > >> >> } > >> >> > >> >> +static bool vtd_process_device_piotlb_desc(IntelIOMMUState *s, > >> >> + VTDInvDesc *inv_desc) > >> >> +{ > >> >> + uint16_t sid; > >> >> + VTDAddressSpace *vtd_dev_as; > >> >> + bool size; > >> >> + bool global; > >> >> + hwaddr addr; > >> >> + uint32_t pasid; > >> >> + > >> >> + if ((inv_desc->hi & VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_HI) |= | > >> >> + (inv_desc->lo & VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_LO))= { > >> >> + error_report_once("%s: invalid pasid-based dev iotlb inv d= esc:" > >> >> + "hi=3D%"PRIx64 "(reserved nonzero)", > >> >> + __func__, inv_desc->hi); > >> >> + return false; > >> >> + } > >> >> + > >> >> + global =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(inv_desc->hi= ); > >> >> + size =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(inv_desc->hi); > >> >> + addr =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(inv_desc->hi); > >> >> + sid =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(inv_desc->lo); > >> >> + if (global) { > >> >> + QLIST_FOREACH(vtd_dev_as, &s->vtd_as_with_notifiers, next)= { > >> >> + if ((vtd_dev_as->pasid !=3D PCI_NO_PASID) && > >> >> + (PCI_BUILD_BDF(pci_bus_num(vtd_dev_as->bus), > >> >> + vtd_dev_as->devfn) =3D= =3D sid)) { > >> >> + do_invalidate_device_tlb(vtd_dev_as, size, addr); > >> >> + } > >> >> + } > >> >> + } else { > >> >> + pasid =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(inv_desc->= lo); > >> >> + vtd_dev_as =3D vtd_get_as_by_sid_and_pasid(s, sid, pasid); > >> >> + if (!vtd_dev_as) { > >> >> + return true; > >> >> + } > >> >> + > >> >> + do_invalidate_device_tlb(vtd_dev_as, size, addr); > >> > > >> >Question: > >> > > >> >I wonder if current vhost (which has a device IOTLB abstraction via > >> >virtio-pci) can work with this (PASID based IOTLB invalidation) > >> > >> Currently, it depends on if caching-mode is on. If it's off, vhost wor= ks. E.g.: > >> > >> -device intel-iommu,caching-mode=3Doff,dma-drain=3Don,device-iotlb=3Do= n,x- > >scalable-mode=3Don > >> -netdev tap,id=3Dtap0,vhost=3Don,script=3D/etc/qemu-ifup > >> -device virtio-net-pci,netdev=3Dtap0,bus=3Droot0,iommu_platform=3Don,a= ts=3Don > >> > >> It doesn't work currently when caching-mode is on. > >> Reason is linux kernel has an optimization to send only piotlb invalid= ation, > >> no device-piotlb invalidation is sent. But I heard from Yi the optimiz= ation > >> will be dropped, then it will work too when caching-mode is on. > > > >Great, if possible please copy me when sending those fixes. > > FYI, I just found the optimization had already been dropped since April 2= 024 by commit https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linu= x.git/commit/?id=3D304b3bde24b58515a75fd198beb52ca57df6275f > > After updating guest kernel to a new version containing above commit, > vhost works irrespective the value of caching-mode. > > Thanks > Zhenzhong Great. Thanks for the updating.