From: Jason Wang <jasowang@redhat.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>
Cc: qemu-devel@nongnu.org, alex.williamson@redhat.com,
clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,
peterx@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,
joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com,
kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: Re: [PATCH v3 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation
Date: Fri, 27 Sep 2024 12:07:59 +0800 [thread overview]
Message-ID: <CACGkMEvN6gHjuoeHtZWLwKXUpDNqWZCGcFnGwhJRRy64XL9ZkA@mail.gmail.com> (raw)
In-Reply-To: <20240911052255.1294071-10-zhenzhong.duan@intel.com>
On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan <zhenzhong.duan@intel.com> wrote:
>
> According to spec, Page-Selective-within-Domain Invalidation (11b):
>
> 1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through
> (PGTT=100b) mappings associated with the specified domain-id and the
> input-address range are invalidated.
> 2. IOTLB entries caching first-stage (PGTT=001b) or nested (PGTT=011b)
> mapping associated with specified domain-id are invalidated.
>
> So per spec definition the Page-Selective-within-Domain Invalidation
> needs to flush first stage and nested cached IOTLB enties as well.
>
> We don't support nested yet and pass-through mapping is never cached,
> so what in iotlb cache are only first-stage and second-stage mappings.
>
> Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and
> invalidate entries based on PGTT type.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
> ---
Acked-by: Jason Wang <jasowang@redhat.com>
Thanks
next prev parent reply other threads:[~2024-09-27 4:09 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-11 5:22 [PATCH v3 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-09-11 5:22 ` [PATCH v3 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-09-27 0:12 ` Jason Wang
2024-09-11 5:22 ` [PATCH v3 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-09-27 0:13 ` Jason Wang
2024-09-11 5:22 ` [PATCH v3 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-09-11 6:26 ` CLEMENT MATHIEU--DRIF
2024-09-11 8:38 ` Duan, Zhenzhong
2024-09-27 0:15 ` Jason Wang
2024-09-11 5:22 ` [PATCH v3 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-09-11 6:54 ` CLEMENT MATHIEU--DRIF
2024-09-27 3:47 ` Jason Wang
2024-09-27 6:38 ` Duan, Zhenzhong
2024-09-11 5:22 ` [PATCH v3 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-09-27 3:47 ` Jason Wang
2024-09-29 12:43 ` Yi Liu
2024-09-30 3:43 ` Duan, Zhenzhong
2024-09-11 5:22 ` [PATCH v3 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-09-27 4:07 ` Jason Wang
2024-09-29 13:58 ` Yi Liu
2024-09-30 5:55 ` Duan, Zhenzhong
2024-09-11 5:22 ` [PATCH v3 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-09-27 4:07 ` Jason Wang
2024-09-11 5:22 ` [PATCH v3 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-09-27 4:07 ` Jason Wang
2024-09-27 6:38 ` Duan, Zhenzhong
2024-09-11 5:22 ` [PATCH v3 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-09-27 4:07 ` Jason Wang [this message]
2024-09-11 5:22 ` [PATCH v3 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-09-27 4:08 ` Jason Wang
2024-09-11 5:22 ` [PATCH v3 11/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-09-27 4:08 ` Jason Wang
2024-09-11 5:22 ` [PATCH v3 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-09-27 4:08 ` Jason Wang
2024-09-27 7:17 ` Duan, Zhenzhong
2024-09-27 8:02 ` Duan, Zhenzhong
2024-09-29 1:59 ` Jason Wang
2024-09-29 2:22 ` Duan, Zhenzhong
2024-12-16 8:21 ` Duan, Zhenzhong
2024-12-17 2:13 ` Jason Wang
2024-12-17 6:06 ` CLEMENT MATHIEU--DRIF
2024-09-11 5:22 ` [PATCH v3 13/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-09-11 5:22 ` [PATCH v3 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode Zhenzhong Duan
2024-09-27 4:08 ` Jason Wang
2024-09-27 6:38 ` Duan, Zhenzhong
2024-09-29 2:02 ` Jason Wang
2024-09-29 2:57 ` Duan, Zhenzhong
2024-09-11 5:22 ` [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose " Zhenzhong Duan
2024-09-11 6:54 ` CLEMENT MATHIEU--DRIF
2024-09-27 4:08 ` Jason Wang
2024-09-27 6:39 ` Duan, Zhenzhong
2024-09-29 2:00 ` Jason Wang
2024-09-29 2:44 ` Duan, Zhenzhong
2024-11-04 3:24 ` Yi Liu
2024-11-04 7:13 ` CLEMENT MATHIEU--DRIF
2024-09-11 5:22 ` [PATCH v3 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-09-27 4:08 ` Jason Wang
2024-09-27 6:39 ` Duan, Zhenzhong
2024-09-11 5:22 ` [PATCH v3 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-09-27 4:08 ` Jason Wang
2024-09-11 6:56 ` [PATCH v3 00/17] intel_iommu: Enable stage-1 translation for emulated device CLEMENT MATHIEU--DRIF
2024-09-11 8:43 ` Duan, Zhenzhong
2024-09-11 10:43 ` Michael S. Tsirkin
2024-09-26 9:25 ` Duan, Zhenzhong
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