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Thu, 26 Sep 2024 21:08:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG7ONwEGYQvT5BBjI+rRKYZNPQDO//6uQgLqdEzAZYSWrTt4OwCidrkXX1+JI/pxuua/6Y3fAP361N8v75bdDY= X-Received: by 2002:a17:90a:bf03:b0:2dd:6969:208e with SMTP id 98e67ed59e1d1-2e0b899c3admr2379691a91.3.1727410092905; Thu, 26 Sep 2024 21:08:12 -0700 (PDT) MIME-Version: 1.0 References: <20240911052255.1294071-1-zhenzhong.duan@intel.com> <20240911052255.1294071-10-zhenzhong.duan@intel.com> In-Reply-To: <20240911052255.1294071-10-zhenzhong.duan@intel.com> From: Jason Wang Date: Fri, 27 Sep 2024 12:07:59 +0800 Message-ID: Subject: Re: [PATCH v3 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation To: Zhenzhong Duan Cc: qemu-devel@nongnu.org, alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.131, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Sep 11, 2024 at 1:26=E2=80=AFPM Zhenzhong Duan wrote: > > According to spec, Page-Selective-within-Domain Invalidation (11b): > > 1. IOTLB entries caching second-stage mappings (PGTT=3D010b) or pass-thro= ugh > (PGTT=3D100b) mappings associated with the specified domain-id and the > input-address range are invalidated. > 2. IOTLB entries caching first-stage (PGTT=3D001b) or nested (PGTT=3D011b= ) > mapping associated with specified domain-id are invalidated. > > So per spec definition the Page-Selective-within-Domain Invalidation > needs to flush first stage and nested cached IOTLB enties as well. > > We don't support nested yet and pass-through mapping is never cached, > so what in iotlb cache are only first-stage and second-stage mappings. > > Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and > invalidate entries based on PGTT type. > > Signed-off-by: Zhenzhong Duan > Reviewed-by: Cl=C3=A9ment Mathieu--Drif > --- Acked-by: Jason Wang Thanks