* [PATCH for-6.0 0/2] aspeed/smc: Extend support
@ 2020-11-20 16:15 Cédric Le Goater
2020-11-20 16:15 ` [PATCH for-6.0 1/2] aspeed/smc: Add support for address lane disablement Cédric Le Goater
2020-11-20 16:15 ` [PATCH for-6.0 2/2] aspeed/smc: Add extra controls to request DMA Cédric Le Goater
0 siblings, 2 replies; 6+ messages in thread
From: Cédric Le Goater @ 2020-11-20 16:15 UTC (permalink / raw)
To: qemu-devel
Cc: Andrew Jeffery, Peter Maydell, qemu-arm, Joel Stanley,
Cédric Le Goater
Hello,
These extensions are required to support the new SPI driver proposed
by Chin-Ting Kuo from Aspeed :
https://lore.kernel.org/linux-spi/20201105120331.9853-1-chin-ting_kuo@aspeedtech.com/T/#mf495e230e7dde8f91cf3a485b0a7293e9db54d32
Thanks,
C.
Cédric Le Goater (2):
aspeed/smc: Add support for address lane disablement
aspeed/smc: Add extra controls to request DMA
hw/ssi/aspeed_smc.c | 32 +++++++++++++++++++++++++-------
1 file changed, 25 insertions(+), 7 deletions(-)
--
2.26.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH for-6.0 1/2] aspeed/smc: Add support for address lane disablement
2020-11-20 16:15 [PATCH for-6.0 0/2] aspeed/smc: Extend support Cédric Le Goater
@ 2020-11-20 16:15 ` Cédric Le Goater
2020-11-25 2:52 ` Joel Stanley
2020-11-20 16:15 ` [PATCH for-6.0 2/2] aspeed/smc: Add extra controls to request DMA Cédric Le Goater
1 sibling, 1 reply; 6+ messages in thread
From: Cédric Le Goater @ 2020-11-20 16:15 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andrew Jeffery, Chin-Ting Kuo, qemu-arm,
Joel Stanley, Cédric Le Goater
The controller can be configured to disable or enable address and data
byte lanes when issuing commands. This is useful in read command mode
to send SPI NOR commands that don't have an address space, such as
RDID. It's a good way to have a unified read operation for registers
and flash contents accesses.
A new SPI driver proposed by Aspeed makes use of this feature. Add
support for address lanes to start with. We will do the same for the
data lanes if they are controlled one day.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ssi/aspeed_smc.c | 25 ++++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 795784e5f364..e3d5e26058c0 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -71,6 +71,16 @@
#define INTR_CTRL_CMD_ABORT_EN (1 << 2)
#define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
+/* Command Control Register */
+#define R_CE_CMD_CTRL (0x0C / 4)
+#define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4
+#define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
+
+#define aspeed_smc_addr_byte_enabled(s, i) \
+ (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
+#define aspeed_smc_data_byte_enabled(s, i) \
+ (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
+
/* CEx Control Register */
#define R_CTRL0 (0x10 / 4)
#define CTRL_IO_QPI (1 << 31)
@@ -702,19 +712,17 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
{
const AspeedSMCState *s = fl->controller;
uint8_t cmd = aspeed_smc_flash_cmd(fl);
- int i;
+ int i = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
/* Flash access can not exceed CS segment */
addr = aspeed_smc_check_segment_addr(fl, addr);
ssi_transfer(s->spi, cmd);
-
- if (aspeed_smc_flash_is_4byte(fl)) {
- ssi_transfer(s->spi, (addr >> 24) & 0xff);
+ while (i--) {
+ if (aspeed_smc_addr_byte_enabled(s, i)) {
+ ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff);
+ }
}
- ssi_transfer(s->spi, (addr >> 16) & 0xff);
- ssi_transfer(s->spi, (addr >> 8) & 0xff);
- ssi_transfer(s->spi, (addr & 0xff));
/*
* Use fake transfers to model dummy bytes. The value should
@@ -988,6 +996,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
(addr >= s->r_timings &&
addr < s->r_timings + s->ctrl->nregs_timings) ||
addr == s->r_ce_ctrl ||
+ addr == R_CE_CMD_CTRL ||
addr == R_INTR_CTRL ||
addr == R_DUMMY_DATA ||
(s->ctrl->has_dma && addr == R_DMA_CTRL) ||
@@ -1276,6 +1285,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
if (value != s->regs[R_SEG_ADDR0 + cs]) {
aspeed_smc_flash_set_segment(s, cs, value);
}
+ } else if (addr == R_CE_CMD_CTRL) {
+ s->regs[addr] = value & 0xff;
} else if (addr == R_DUMMY_DATA) {
s->regs[addr] = value & 0xff;
} else if (addr == R_INTR_CTRL) {
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH for-6.0 2/2] aspeed/smc: Add extra controls to request DMA
2020-11-20 16:15 [PATCH for-6.0 0/2] aspeed/smc: Extend support Cédric Le Goater
2020-11-20 16:15 ` [PATCH for-6.0 1/2] aspeed/smc: Add support for address lane disablement Cédric Le Goater
@ 2020-11-20 16:15 ` Cédric Le Goater
2020-11-25 2:49 ` Joel Stanley
1 sibling, 1 reply; 6+ messages in thread
From: Cédric Le Goater @ 2020-11-20 16:15 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Andrew Jeffery, Chin-Ting Kuo, qemu-arm,
Joel Stanley, Cédric Le Goater
The controller has a set of hidden bits to request/grant DMA access.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ssi/aspeed_smc.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index e3d5e26058c0..c1557ef5d848 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -127,6 +127,8 @@
/* DMA Control/Status Register */
#define R_DMA_CTRL (0x80 / 4)
+#define DMA_CTRL_REQUEST (1 << 31)
+#define DMA_CTRL_GRANT (1 << 30)
#define DMA_CTRL_DELAY_MASK 0xf
#define DMA_CTRL_DELAY_SHIFT 8
#define DMA_CTRL_FREQ_MASK 0xf
@@ -1237,6 +1239,11 @@ static void aspeed_smc_dma_done(AspeedSMCState *s)
static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
{
+ if (dma_ctrl & DMA_CTRL_REQUEST) {
+ s->regs[R_DMA_CTRL] = dma_ctrl | DMA_CTRL_GRANT;
+ return;
+ }
+
if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
s->regs[R_DMA_CTRL] = dma_ctrl;
--
2.26.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH for-6.0 2/2] aspeed/smc: Add extra controls to request DMA
2020-11-20 16:15 ` [PATCH for-6.0 2/2] aspeed/smc: Add extra controls to request DMA Cédric Le Goater
@ 2020-11-25 2:49 ` Joel Stanley
2020-11-25 7:48 ` Cédric Le Goater
0 siblings, 1 reply; 6+ messages in thread
From: Joel Stanley @ 2020-11-25 2:49 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Andrew Jeffery, Peter Maydell, Chin-Ting Kuo, qemu-arm,
QEMU Developers
On Fri, 20 Nov 2020 at 16:16, Cédric Le Goater <clg@kaod.org> wrote:
>
> The controller has a set of hidden bits to request/grant DMA access.
Do you have the ast2600 datasheet? It describes these bits:
31 RW DMA Request
Write SPIR80 = 0xAEED0000 to set this bit ot '1'.
And hardware will clear the request to '0' after DMA done, or FW can
clear to '0' by writing SPIR80 = 0xDEEA0000.
30 RO DMA Grant
0: DMA is not allowed to be used. All DMA related control registers
are not allowed to be written.
1: DMA is granted to be used.
Do you want to add the magic behavior to your model?
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ssi/aspeed_smc.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index e3d5e26058c0..c1557ef5d848 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -127,6 +127,8 @@
>
> /* DMA Control/Status Register */
> #define R_DMA_CTRL (0x80 / 4)
> +#define DMA_CTRL_REQUEST (1 << 31)
> +#define DMA_CTRL_GRANT (1 << 30)
> #define DMA_CTRL_DELAY_MASK 0xf
> #define DMA_CTRL_DELAY_SHIFT 8
> #define DMA_CTRL_FREQ_MASK 0xf
> @@ -1237,6 +1239,11 @@ static void aspeed_smc_dma_done(AspeedSMCState *s)
>
> static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
> {
> + if (dma_ctrl & DMA_CTRL_REQUEST) {
> + s->regs[R_DMA_CTRL] = dma_ctrl | DMA_CTRL_GRANT;
> + return;
> + }
> +
> if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
> s->regs[R_DMA_CTRL] = dma_ctrl;
>
> --
> 2.26.2
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH for-6.0 1/2] aspeed/smc: Add support for address lane disablement
2020-11-20 16:15 ` [PATCH for-6.0 1/2] aspeed/smc: Add support for address lane disablement Cédric Le Goater
@ 2020-11-25 2:52 ` Joel Stanley
0 siblings, 0 replies; 6+ messages in thread
From: Joel Stanley @ 2020-11-25 2:52 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Andrew Jeffery, Peter Maydell, Chin-Ting Kuo, qemu-arm,
QEMU Developers
On Fri, 20 Nov 2020 at 16:16, Cédric Le Goater <clg@kaod.org> wrote:
>
> The controller can be configured to disable or enable address and data
> byte lanes when issuing commands. This is useful in read command mode
> to send SPI NOR commands that don't have an address space, such as
> RDID. It's a good way to have a unified read operation for registers
> and flash contents accesses.
>
> A new SPI driver proposed by Aspeed makes use of this feature. Add
> support for address lanes to start with. We will do the same for the
> data lanes if they are controlled one day.
>
> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> hw/ssi/aspeed_smc.c | 25 ++++++++++++++++++-------
> 1 file changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index 795784e5f364..e3d5e26058c0 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -71,6 +71,16 @@
> #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
> #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
>
> +/* Command Control Register */
> +#define R_CE_CMD_CTRL (0x0C / 4)
> +#define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4
> +#define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
> +
> +#define aspeed_smc_addr_byte_enabled(s, i) \
> + (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
> +#define aspeed_smc_data_byte_enabled(s, i) \
> + (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
> +
> /* CEx Control Register */
> #define R_CTRL0 (0x10 / 4)
> #define CTRL_IO_QPI (1 << 31)
> @@ -702,19 +712,17 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
> {
> const AspeedSMCState *s = fl->controller;
> uint8_t cmd = aspeed_smc_flash_cmd(fl);
> - int i;
> + int i = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
>
> /* Flash access can not exceed CS segment */
> addr = aspeed_smc_check_segment_addr(fl, addr);
>
> ssi_transfer(s->spi, cmd);
> -
> - if (aspeed_smc_flash_is_4byte(fl)) {
> - ssi_transfer(s->spi, (addr >> 24) & 0xff);
> + while (i--) {
> + if (aspeed_smc_addr_byte_enabled(s, i)) {
> + ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff);
> + }
> }
> - ssi_transfer(s->spi, (addr >> 16) & 0xff);
> - ssi_transfer(s->spi, (addr >> 8) & 0xff);
> - ssi_transfer(s->spi, (addr & 0xff));
>
> /*
> * Use fake transfers to model dummy bytes. The value should
> @@ -988,6 +996,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
> (addr >= s->r_timings &&
> addr < s->r_timings + s->ctrl->nregs_timings) ||
> addr == s->r_ce_ctrl ||
> + addr == R_CE_CMD_CTRL ||
> addr == R_INTR_CTRL ||
> addr == R_DUMMY_DATA ||
> (s->ctrl->has_dma && addr == R_DMA_CTRL) ||
> @@ -1276,6 +1285,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
> if (value != s->regs[R_SEG_ADDR0 + cs]) {
> aspeed_smc_flash_set_segment(s, cs, value);
> }
> + } else if (addr == R_CE_CMD_CTRL) {
> + s->regs[addr] = value & 0xff;
> } else if (addr == R_DUMMY_DATA) {
> s->regs[addr] = value & 0xff;
> } else if (addr == R_INTR_CTRL) {
> --
> 2.26.2
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH for-6.0 2/2] aspeed/smc: Add extra controls to request DMA
2020-11-25 2:49 ` Joel Stanley
@ 2020-11-25 7:48 ` Cédric Le Goater
0 siblings, 0 replies; 6+ messages in thread
From: Cédric Le Goater @ 2020-11-25 7:48 UTC (permalink / raw)
To: Joel Stanley
Cc: Andrew Jeffery, Peter Maydell, Chin-Ting Kuo, qemu-arm,
QEMU Developers
On 11/25/20 3:49 AM, Joel Stanley wrote:
> On Fri, 20 Nov 2020 at 16:16, Cédric Le Goater <clg@kaod.org> wrote:
>>
>> The controller has a set of hidden bits to request/grant DMA access.
>
> Do you have the ast2600 datasheet? It describes these bits:
>
> 31 RW DMA Request
>
> Write SPIR80 = 0xAEED0000 to set this bit ot '1'.
> And hardware will clear the request to '0' after DMA done, or FW can
> clear to '0' by writing SPIR80 = 0xDEEA0000.
>
> 30 RO DMA Grant
>
> 0: DMA is not allowed to be used. All DMA related control registers
> are not allowed to be written.
> 1: DMA is granted to be used.
I see them now :) They are under the SPI controllers but not under
the BMC SPI controller where I was looking. May be the datasheet
was updated now ?
> Do you want to add the magic behavior to your model?
Yes. The Aspeed SPI driver needs them. I think the model can be better.
I will send a v2.
Thanks,
C.
>
>>
>> Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ssi/aspeed_smc.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
>> index e3d5e26058c0..c1557ef5d848 100644
>> --- a/hw/ssi/aspeed_smc.c
>> +++ b/hw/ssi/aspeed_smc.c
>> @@ -127,6 +127,8 @@
>>
>> /* DMA Control/Status Register */
>> #define R_DMA_CTRL (0x80 / 4)
>> +#define DMA_CTRL_REQUEST (1 << 31)
>> +#define DMA_CTRL_GRANT (1 << 30)
>> #define DMA_CTRL_DELAY_MASK 0xf
>> #define DMA_CTRL_DELAY_SHIFT 8
>> #define DMA_CTRL_FREQ_MASK 0xf
>> @@ -1237,6 +1239,11 @@ static void aspeed_smc_dma_done(AspeedSMCState *s)
>>
>> static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
>> {
>> + if (dma_ctrl & DMA_CTRL_REQUEST) {
>> + s->regs[R_DMA_CTRL] = dma_ctrl | DMA_CTRL_GRANT;
>> + return;
>> + }
>> +
>> if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
>> s->regs[R_DMA_CTRL] = dma_ctrl;
>>
>> --
>> 2.26.2
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-11-25 7:49 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-11-20 16:15 [PATCH for-6.0 0/2] aspeed/smc: Extend support Cédric Le Goater
2020-11-20 16:15 ` [PATCH for-6.0 1/2] aspeed/smc: Add support for address lane disablement Cédric Le Goater
2020-11-25 2:52 ` Joel Stanley
2020-11-20 16:15 ` [PATCH for-6.0 2/2] aspeed/smc: Add extra controls to request DMA Cédric Le Goater
2020-11-25 2:49 ` Joel Stanley
2020-11-25 7:48 ` Cédric Le Goater
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