From: Artyom Tarasenko <atar4qemu@gmail.com>
To: Richard Henderson <rth@twiddle.net>
Cc: qemu-devel <qemu-devel@nongnu.org>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: Re: [Qemu-devel] [PATCH v3 00/15] target-sparc improvements
Date: Mon, 31 Oct 2016 16:40:31 +0100 [thread overview]
Message-ID: <CACXAS8APkbcL=mzfDPeJM6jaAjPbdc55FZ9_Rg=RnBttTihJ0A@mail.gmail.com> (raw)
In-Reply-To: <1477588052-10152-1-git-send-email-rth@twiddle.net>
On Thu, Oct 27, 2016 at 7:07 PM, Richard Henderson <rth@twiddle.net> wrote:
> The two main goals in this patch set are:
> * Make use of the new MO_ALIGN_* flags, to allow less use of check_align,
> and support partially misaligned fp memory ops.
> * More cleanups for ASIs, in the end using the new atomic ops.
>
> Changes since v2:
> * Rebased on master with the atomic patches merged; one minor conflict fixed.
> * In patch 11, move and simplify address_mask. It's no longer used
> at all by sparc32 and clang warned about the unused inline function.
>
> Changes since v1:
> * The "Remove asi helper code handled inline" patch retains the code within
> ldda to handle asis that must be handled out of line. This fixes the
> FreeBSD 10.3 boot problem. While the UA2007 spec (and thus sun4v?) doesn't
> allow for such, it would seem that US2 hardware does.
What ASI was failing? It may still be a part of sun4v CPUs if it's
described in UST1/UST2 supplements.
I think some instructions didn't make it into UA20xx standard specs
because of some Sun patents
--
Regards,
Artyom Tarasenko
SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
next prev parent reply other threads:[~2016-10-31 15:40 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-27 17:07 [Qemu-devel] [PATCH v3 00/15] target-sparc improvements Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 01/15] target-sparc: Use overalignment flags for twinx and block asis Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 02/15] target-sparc: Introduce cpu_raise_exception_ra Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 03/15] target-sparc: Add MMU_PHYS_IDX Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 05/15] target-sparc: Handle more twinx asis Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 06/15] target-sparc: Implement swap_asi inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 07/15] target-sparc: Implement ldstub_asi inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 08/15] target-sparc: Implement cas_asi/casx_asi inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 09/15] target-sparc: Implement BCOPY/BFILL inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 10/15] target-sparc: Remove asi helper code handled inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 11/15] target-sparc: Implement ldqf and stqf inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 12/15] target-sparc: Allow 4-byte alignment on fp mem ops Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 13/15] target-sparc: Remove MMU_MODE*_SUFFIX Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 14/15] target-sparc: Use tcg_gen_atomic_xchg_tl Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 15/15] target-sparc: Use tcg_gen_atomic_cmpxchg_tl Richard Henderson
2016-10-28 14:22 ` [Qemu-devel] [PATCH v3 00/15] target-sparc improvements Mark Cave-Ayland
2016-10-31 15:40 ` Artyom Tarasenko [this message]
2016-10-31 16:06 ` Richard Henderson
2016-10-31 16:21 ` Artyom Tarasenko
2016-10-31 16:32 ` Richard Henderson
2016-10-31 17:31 ` Artyom Tarasenko
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