From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54675) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c1Ehm-0006gf-EV for qemu-devel@nongnu.org; Mon, 31 Oct 2016 11:40:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c1Ehi-0005or-Hn for qemu-devel@nongnu.org; Mon, 31 Oct 2016 11:40:58 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:34451) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c1Ehi-0005ny-9p for qemu-devel@nongnu.org; Mon, 31 Oct 2016 11:40:54 -0400 Received: by mail-lf0-x243.google.com with SMTP id i187so7310837lfe.1 for ; Mon, 31 Oct 2016 08:40:53 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1477588052-10152-1-git-send-email-rth@twiddle.net> References: <1477588052-10152-1-git-send-email-rth@twiddle.net> From: Artyom Tarasenko Date: Mon, 31 Oct 2016 16:40:31 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v3 00/15] target-sparc improvements List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel , Mark Cave-Ayland On Thu, Oct 27, 2016 at 7:07 PM, Richard Henderson wrote: > The two main goals in this patch set are: > * Make use of the new MO_ALIGN_* flags, to allow less use of check_align, > and support partially misaligned fp memory ops. > * More cleanups for ASIs, in the end using the new atomic ops. > > Changes since v2: > * Rebased on master with the atomic patches merged; one minor conflict fixed. > * In patch 11, move and simplify address_mask. It's no longer used > at all by sparc32 and clang warned about the unused inline function. > > Changes since v1: > * The "Remove asi helper code handled inline" patch retains the code within > ldda to handle asis that must be handled out of line. This fixes the > FreeBSD 10.3 boot problem. While the UA2007 spec (and thus sun4v?) doesn't > allow for such, it would seem that US2 hardware does. What ASI was failing? It may still be a part of sun4v CPUs if it's described in UST1/UST2 supplements. I think some instructions didn't make it into UA20xx standard specs because of some Sun patents -- Regards, Artyom Tarasenko SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu