From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:51002) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UY14L-0002tj-Vd for qemu-devel@nongnu.org; Thu, 02 May 2013 17:29:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UY14K-0007p8-1j for qemu-devel@nongnu.org; Thu, 02 May 2013 17:29:37 -0400 MIME-Version: 1.0 In-Reply-To: <1367525344-7755-5-git-send-email-hpoussin@reactos.org> References: <1367525344-7755-1-git-send-email-hpoussin@reactos.org> <1367525344-7755-5-git-send-email-hpoussin@reactos.org> From: Artyom Tarasenko Date: Thu, 2 May 2013 23:29:12 +0200 Message-ID: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 4/7] m48t59: register a QOM type for each nvram type we support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-1?Q?Herv=E9_Poussineau?= , Blue Swirl Cc: qemu-ppc@nongnu.org, qemu-devel , =?ISO-8859-1?Q?Andreas_F=E4rber?= On Thu, May 2, 2013 at 10:09 PM, Herv=E9 Poussineau = wrote: > As m48t59 devices can only be created with m48t59_init() or m48t59_init_i= sa(), > we know exactly which nvram types are required. Register only those three > types. Wasn't this patch NACKed by Blue? > Remove .model and .size properties as they can be infered from nvram name= . > > Rename type to 'isa-*' (and 'sysbus-*') to do like other devices ISA devi= ces > (isa-ide, isa-parallel, isa-serial...) > > Signed-off-by: Herv=E9 Poussineau > --- > hw/timer/m48t59.c | 248 +++++++++++++++++++++++++++++++++++++----------= ------ > 1 file changed, 172 insertions(+), 76 deletions(-) > > diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c > index fb78d20..23a6ab3 100644 > --- a/hw/timer/m48t59.c > +++ b/hw/timer/m48t59.c > @@ -2,6 +2,7 @@ > * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platfor= ms > * > * Copyright (c) 2003-2005, 2007 Jocelyn Mayer > + * Copyright (c) 2013 Herv=E9 Poussineau > * > * Permission is hereby granted, free of charge, to any person obtaining= a copy > * of this software and associated documentation files (the "Software"),= to deal > @@ -37,12 +38,31 @@ > #define NVRAM_PRINTF(fmt, ...) do { } while (0) > #endif > > +#define TYPE_M48TXX_SYS_BUS "m48txx-sysbus" > +#define M48TXX_SYS_BUS_CLASS(klass) \ > + OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS= _BUS) > +#define M48TXX_SYS_BUS(obj) \ > + OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS) > + > +#define TYPE_M48TXX_ISA "m48txx-isa" > +#define M48TXX_ISA_CLASS(klass) \ > + OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA) > +#define M48TXX_ISA(obj) \ > + OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA) > + > /* > * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 h= as > * alarm and a watchdog timer and related control registers. In the > * PPC platform there is also a nvram lock function. > */ > > +typedef struct M48txxInfo { > + const char *isa_name; > + const char *sysbus_name; > + uint32_t model; /* 2 =3D m48t02, 8 =3D m48t08, 59 =3D m48t59 */ > + uint32_t size; > +} M48txxInfo; > + > /* > * Chipset docs: > * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf > @@ -54,7 +74,6 @@ struct M48t59State { > /* Hardware parameters */ > qemu_irq IRQ; > MemoryRegion iomem; > - uint32_t io_base; > uint32_t size; > /* RTC management */ > time_t time_offset; > @@ -72,22 +91,45 @@ struct M48t59State { > uint8_t lock; > }; > > -#define TYPE_ISA_M48T59 "m48t59_isa" > -#define ISA_M48T59(obj) \ > - OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59) > - > -typedef struct M48t59ISAState { > +typedef struct M48txxISAState { > ISADevice parent_obj; > - > M48t59State state; > + uint32_t io_base; > MemoryRegion io; > -} M48t59ISAState; > +} M48txxISAState; > + > +typedef struct M48txxISADeviceClass { > + ISADeviceClass parent_class; > + M48txxInfo info; > +} M48txxISADeviceClass; > > -typedef struct M48t59SysBusState { > - SysBusDevice busdev; > +typedef struct M48txxSysBusState { > + SysBusDevice parent_obj; > M48t59State state; > MemoryRegion io; > -} M48t59SysBusState; > +} M48txxSysBusState; > + > +typedef struct M48txxSysBusDeviceClass { > + SysBusDeviceClass parent_class; > + M48txxInfo info; > +} M48txxSysBusDeviceClass; > + > +static M48txxInfo m48txx_info[] =3D { > + { > + .sysbus_name =3D "sysbus-m48t02", > + .model =3D 2, > + .size =3D 0x800, > + },{ > + .sysbus_name =3D "sysbus-m48t08", > + .model =3D 8, > + .size =3D 0x2000, > + },{ > + .isa_name =3D "isa-m48t59", > + .model =3D 59, > + .size =3D 0x2000, > + } > +}; > + > > /* Fake timer functions */ > > @@ -613,7 +655,7 @@ static void m48t59_reset_common(M48t59State *NVRAM) > > static void m48t59_reset_isa(DeviceState *d) > { > - M48t59ISAState *isa =3D ISA_M48T59(d); > + M48txxISAState *isa =3D M48TXX_ISA(d); > M48t59State *NVRAM =3D &isa->state; > > m48t59_reset_common(NVRAM); > @@ -621,7 +663,7 @@ static void m48t59_reset_isa(DeviceState *d) > > static void m48t59_reset_sysbus(DeviceState *d) > { > - M48t59SysBusState *sys =3D container_of(d, M48t59SysBusState, busdev= .qdev); > + M48txxSysBusState *sys =3D M48TXX_SYS_BUS(d); > M48t59State *NVRAM =3D &sys->state; > > m48t59_reset_common(NVRAM); > @@ -643,47 +685,62 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_b= ase, > { > DeviceState *dev; > SysBusDevice *s; > - M48t59SysBusState *d; > + M48txxSysBusState *d; > M48t59State *state; > + int i; > > - dev =3D qdev_create(NULL, "m48t59"); > - qdev_prop_set_uint32(dev, "model", model); > - qdev_prop_set_uint32(dev, "size", size); > - qdev_prop_set_uint32(dev, "io_base", io_base); > - qdev_init_nofail(dev); > - s =3D SYS_BUS_DEVICE(dev); > - d =3D FROM_SYSBUS(M48t59SysBusState, s); > - state =3D &d->state; > - sysbus_connect_irq(s, 0, IRQ); > - if (io_base !=3D 0) { > - memory_region_add_subregion(get_system_io(), io_base, > - sysbus_mmio_get_region(dev, 1)); > - } > - if (mem_base !=3D 0) { > - sysbus_mmio_map(s, 0, mem_base); > + for (i =3D 0; i < ARRAY_SIZE(m48txx_info); i++) { > + if (!m48txx_info[i].sysbus_name || > + m48txx_info[i].size !=3D size || > + m48txx_info[i].model !=3D model) { > + continue; > + } > + > + dev =3D qdev_create(NULL, m48txx_info[i].sysbus_name); > + qdev_init_nofail(dev); > + s =3D SYS_BUS_DEVICE(dev); > + d =3D M48TXX_SYS_BUS(s); > + state =3D &d->state; > + sysbus_connect_irq(s, 0, IRQ); > + memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4= ); > + if (io_base !=3D 0) { > + memory_region_add_subregion(get_system_io(), io_base, > + sysbus_mmio_get_region(s, 1)); > + } > + if (mem_base !=3D 0) { > + sysbus_mmio_map(s, 0, mem_base); > + } > + > + return state; > } > > - return state; > + assert(false); > + return NULL; > } > > M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t siz= e, > int model) > { > - M48t59ISAState *d; > - ISADevice *isadev; > + M48txxISAState *d; > DeviceState *dev; > - M48t59State *s; > - > - isadev =3D isa_create(bus, TYPE_ISA_M48T59); > - dev =3D DEVICE(isadev); > - qdev_prop_set_uint32(dev, "model", model); > - qdev_prop_set_uint32(dev, "size", size); > - qdev_prop_set_uint32(dev, "io_base", io_base); > - qdev_init_nofail(dev); > - d =3D ISA_M48T59(isadev); > - s =3D &d->state; > - > - return s; > + int i; > + > + for (i =3D 0; i < ARRAY_SIZE(m48txx_info); i++) { > + if (!m48txx_info[i].isa_name || > + m48txx_info[i].size !=3D size || > + m48txx_info[i].model !=3D model) { > + continue; > + } > + > + dev =3D DEVICE(isa_create(bus, m48txx_info[i].isa_name)); > + qdev_prop_set_uint32(dev, "iobase", io_base); > + qdev_init_nofail(dev); > + d =3D container_of(ISA_DEVICE(dev), M48txxISAState, parent_obj); > + return &d->state; > + } > + > + assert(false); > + return NULL; > } > > static void m48t59_init_common(M48t59State *s) > @@ -700,14 +757,19 @@ static void m48t59_init_common(M48t59State *s) > > static int m48t59_init_isa1(ISADevice *dev) > { > - M48t59ISAState *d =3D ISA_M48T59(dev); > + ISADeviceClass *ic =3D ISA_DEVICE_GET_CLASS(dev); > + M48txxISADeviceClass *u =3D container_of(ic, M48txxISADeviceClass, > + parent_class); > + M48txxISAState *d =3D container_of(dev, M48txxISAState, parent_obj); > M48t59State *s =3D &d->state; > > + s->model =3D u->info.model; > + s->size =3D u->info.size; > isa_init_irq(dev, &s->IRQ, 8); > m48t59_init_common(s); > memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); > - if (s->io_base !=3D 0) { > - isa_register_ioport(dev, &d->io, s->io_base); > + if (d->io_base !=3D 0) { > + isa_register_ioport(dev, &d->io, d->io_base); > } > > return 0; > @@ -715,9 +777,14 @@ static int m48t59_init_isa1(ISADevice *dev) > > static int m48t59_init1(SysBusDevice *dev) > { > - M48t59SysBusState *d =3D FROM_SYSBUS(M48t59SysBusState, dev); > + SysBusDeviceClass *k =3D SYS_BUS_DEVICE_GET_CLASS(dev); > + M48txxSysBusDeviceClass *u =3D container_of(k, M48txxSysBusDeviceCla= ss, > + parent_class); > + M48txxSysBusState *d =3D container_of(dev, M48txxSysBusState, parent= _obj); > M48t59State *s =3D &d->state; > > + s->model =3D u->info.model; > + s->size =3D u->info.size; > sysbus_init_irq(dev, &s->IRQ); > > memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->s= ize); > @@ -730,57 +797,86 @@ static int m48t59_init1(SysBusDevice *dev) > } > > static Property m48t59_isa_properties[] =3D { > - DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), > - DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), > - DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), > + DEFINE_PROP_HEX32("iobase", M48txxISAState, io_base, 0x74), > DEFINE_PROP_END_OF_LIST(), > }; > > -static void m48t59_isa_class_init(ObjectClass *klass, void *data) > +static void m48txx_isa_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > ISADeviceClass *ic =3D ISA_DEVICE_CLASS(klass); > + M48txxISADeviceClass *u =3D M48TXX_ISA_CLASS(klass); > + M48txxInfo *info =3D data; > + > ic->init =3D m48t59_init_isa1; > dc->no_user =3D 1; > dc->reset =3D m48t59_reset_isa; > - dc->props =3D m48t59_isa_properties; > + if (info) { > + dc->props =3D m48t59_isa_properties; > + u->info =3D *info; > + } > } > > -static const TypeInfo m48t59_isa_info =3D { > - .name =3D TYPE_ISA_M48T59, > - .parent =3D TYPE_ISA_DEVICE, > - .instance_size =3D sizeof(M48t59ISAState), > - .class_init =3D m48t59_isa_class_init, > -}; > - > -static Property m48t59_properties[] =3D { > - DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), > - DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), > - DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > -static void m48t59_class_init(ObjectClass *klass, void *data) > +static void m48txx_sysbus_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); > + M48txxSysBusDeviceClass *u =3D M48TXX_SYS_BUS_CLASS(klass); > + M48txxInfo *info =3D data; > > k->init =3D m48t59_init1; > dc->reset =3D m48t59_reset_sysbus; > - dc->props =3D m48t59_properties; > + if (info) { > + u->info =3D *info; > + } > } > > -static const TypeInfo m48t59_info =3D { > - .name =3D "m48t59", > - .parent =3D TYPE_SYS_BUS_DEVICE, > - .instance_size =3D sizeof(M48t59SysBusState), > - .class_init =3D m48t59_class_init, > +static const TypeInfo m48txx_sysbus_type_info =3D { > + .name =3D TYPE_M48TXX_SYS_BUS, > + .parent =3D TYPE_SYS_BUS_DEVICE, > + .instance_size =3D sizeof(M48txxSysBusState), > + .abstract =3D true, > + .class_init =3D m48txx_sysbus_class_init, > +}; > + > +static const TypeInfo m48txx_isa_type_info =3D { > + .name =3D TYPE_M48TXX_ISA, > + .parent =3D TYPE_ISA_DEVICE, > + .instance_size =3D sizeof(M48txxISAState), > + .abstract =3D true, > + .class_init =3D m48txx_isa_class_init, > }; > > static void m48t59_register_types(void) > { > - type_register_static(&m48t59_info); > - type_register_static(&m48t59_isa_info); > + TypeInfo sysbus_type_info =3D { > + .parent =3D TYPE_M48TXX_SYS_BUS, > + .class_size =3D sizeof(M48txxSysBusDeviceClass), > + .class_init =3D m48txx_sysbus_class_init, > + }; > + TypeInfo isa_type_info =3D { > + .parent =3D TYPE_M48TXX_ISA, > + .class_size =3D sizeof(M48txxISADeviceClass), > + .class_init =3D m48txx_isa_class_init, > + }; > + int i; > + > + type_register_static(&m48txx_sysbus_type_info); > + type_register_static(&m48txx_isa_type_info); > + > + for (i =3D 0; i < ARRAY_SIZE(m48txx_info); i++) { > + if (m48txx_info[i].sysbus_name) { > + sysbus_type_info.name =3D m48txx_info[i].sysbus_name; > + sysbus_type_info.class_data =3D &m48txx_info[i]; > + type_register(&sysbus_type_info); > + } > + > + if (m48txx_info[i].isa_name) { > + isa_type_info.name =3D m48txx_info[i].isa_name; > + isa_type_info.class_data =3D &m48txx_info[i]; > + type_register(&isa_type_info); > + } > + } > } > > type_init(m48t59_register_types) > -- > 1.7.10.4 > > -- Regards, Artyom Tarasenko linux/sparc and solaris/sparc under qemu blog: http://tyom.blogspot.com/search/label/qemu