From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qn8hb-000170-TW for qemu-devel@nongnu.org; Sat, 30 Jul 2011 08:31:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qn8ha-0004NP-Nx for qemu-devel@nongnu.org; Sat, 30 Jul 2011 08:31:35 -0400 Received: from mail-qy0-f173.google.com ([209.85.216.173]:41128) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qn8ha-0004NG-Kz for qemu-devel@nongnu.org; Sat, 30 Jul 2011 08:31:34 -0400 Received: by qyk10 with SMTP id 10so310550qyk.4 for ; Sat, 30 Jul 2011 05:31:33 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <316f198de781f7b819456f433d84ead284769a71.1311606610.git.atar4qemu@gmail.com> From: Artyom Tarasenko Date: Sat, 30 Jul 2011 14:31:13 +0200 Message-ID: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] fix disabling interrupts in sun4u List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org On Sat, Jul 30, 2011 at 11:09 AM, Blue Swirl wrote: > On Mon, Jul 25, 2011 at 8:22 PM, Artyom Tarasenko w= rote: >> clear interrupt request if the interrupt priority < CPU pil >> clear hardware interrupt request if interrupts are disabled >> >> Signed-off-by: Artyom Tarasenko >> --- >> =A0hw/sun4u.c | =A0 =A06 ++++-- >> =A01 files changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/hw/sun4u.c b/hw/sun4u.c >> index d7dcaf0..7f95aeb 100644 >> --- a/hw/sun4u.c >> +++ b/hw/sun4u.c >> @@ -255,7 +255,7 @@ void cpu_check_irqs(CPUState *env) >> =A0 =A0 =A0 =A0 pil |=3D 1 << 14; >> =A0 =A0 } >> >> - =A0 =A0if (!pil) { >> + =A0 =A0if (pil < (2 << env->psrpil)){ > > Sorry, I don't understand the patch. Where is this '2' coming from? We shouldn't interrupt at levels <=3D psrpil. The bit corresponding to psrpil is (1<< psrpil), the next bit is (2 << psrpil). > >> =A0 =A0 =A0 =A0 if (env->interrupt_request & CPU_INTERRUPT_HARD) { >> =A0 =A0 =A0 =A0 =A0 =A0 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt= %x)\n", >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0env->interrupt_in= dex); >> @@ -287,10 +287,12 @@ void cpu_check_irqs(CPUState *env) >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break; >> =A0 =A0 =A0 =A0 =A0 =A0 } >> =A0 =A0 =A0 =A0 } >> - =A0 =A0} else { >> + =A0 =A0} else if (env->interrupt_request & CPU_INTERRUPT_HARD) { >> =A0 =A0 =A0 =A0 CPUIRQ_DPRINTF("Interrupts disabled, pil=3D%08x pil_in= =3D%08x softint=3D%08x " >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"current interrupt %x\n", >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pil, env->pil_in, env->so= ftint, env->interrupt_index); >> + =A0 =A0 =A0 =A0env->interrupt_index =3D 0; >> + =A0 =A0 =A0 =A0cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); > > Why reset the index? The idea is that the interrupt is left pending a > change to PIL etc. But it is kept in env->pil_in and env->softint . Am I missing some scenario where it's not enough? >> =A0 =A0 } >> =A0} >> >> -- >> 1.7.3.4 >> >> > --=20 Regards, Artyom Tarasenko solaris/sparc under qemu blog: http://tyom.blogspot.com/