From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35151) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCcIK-0001Ur-DT for qemu-devel@nongnu.org; Tue, 27 Mar 2012 15:43:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SCcIF-0003wr-Mv for qemu-devel@nongnu.org; Tue, 27 Mar 2012 15:43:03 -0400 Received: from mail-qc0-f173.google.com ([209.85.216.173]:51738) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCcIF-0003rc-Dy for qemu-devel@nongnu.org; Tue, 27 Mar 2012 15:42:59 -0400 Received: by qcsc20 with SMTP id c20so215864qcs.4 for ; Tue, 27 Mar 2012 12:42:57 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Artyom Tarasenko Date: Tue, 27 Mar 2012 21:42:37 +0200 Message-ID: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] sparc: pass page aligned addresses to tlb_set_page List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Mark Cave-Ayland , Avi Kivity , qemu-devel Since Mark and Avi are keeping silence, Tested-by: Artyom Tarasenko On Sun, Mar 18, 2012 at 12:57 PM, Blue Swirl wrote: > Mask incoming page address early so that resolved addresses > are page aligned. Remove further address masking. > > Signed-off-by: Blue Swirl > --- > =A0target-sparc/mmu_helper.c | =A0 19 ++++++++----------- > =A01 files changed, 8 insertions(+), 11 deletions(-) > > diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c > index 11fb9f5..cb73c44 100644 > --- a/target-sparc/mmu_helper.c > +++ b/target-sparc/mmu_helper.c > @@ -150,18 +150,17 @@ static int get_physical_address(CPUSPARCState > *env, target_phys_addr_t *physical > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case 3: /* Reserved */ > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 return (3 << 8) | (4 << 2); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case 2: /* L3 PTE */ > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0page_offset =3D (address & TARGE= T_PAGE_MASK) & > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(TARGET_PAGE_SIZE - 1); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0page_offset =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 } > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 *page_size =3D TARGET_PAGE_SIZE; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break; > =A0 =A0 =A0 =A0 =A0 =A0 case 2: /* L2 PTE */ > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0page_offset =3D address & 0x3ffff; > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0page_offset =3D address & 0x3f000; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 *page_size =3D 0x40000; > =A0 =A0 =A0 =A0 =A0 =A0 } > =A0 =A0 =A0 =A0 =A0 =A0 break; > =A0 =A0 =A0 =A0 case 2: /* L1 PTE */ > - =A0 =A0 =A0 =A0 =A0 =A0page_offset =3D address & 0xffffff; > + =A0 =A0 =A0 =A0 =A0 =A0page_offset =3D address & 0xfff000; > =A0 =A0 =A0 =A0 =A0 =A0 *page_size =3D 0x1000000; > =A0 =A0 =A0 =A0 } > =A0 =A0 } > @@ -206,11 +205,11 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState > *env, target_ulong address, int rw, > =A0 =A0 target_ulong page_size; > =A0 =A0 int error_code =3D 0, prot, access_index; > > + =A0 =A0address &=3D TARGET_PAGE_MASK; > =A0 =A0 error_code =3D get_physical_address(env, &paddr, &prot, &access_i= ndex, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 address, rw, mmu_idx, &page_size); > + =A0 =A0vaddr =3D address; > =A0 =A0 if (error_code =3D=3D 0) { > - =A0 =A0 =A0 =A0vaddr =3D address & TARGET_PAGE_MASK; > - =A0 =A0 =A0 =A0paddr &=3D TARGET_PAGE_MASK; > =A0#ifdef DEBUG_MMU > =A0 =A0 =A0 =A0 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_pl= x ", vaddr " > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0TARGET_FMT_lx "\n", address, paddr, vaddr)= ; > @@ -230,7 +229,6 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, > target_ulong address, int rw, > =A0 =A0 =A0 =A0 =A0 =A0permissions. If no mapping is available, redirect = accesses to > =A0 =A0 =A0 =A0 =A0 =A0neverland. Fake/overridden mappings will be flushe= d when > =A0 =A0 =A0 =A0 =A0 =A0switching to normal mode. */ > - =A0 =A0 =A0 =A0vaddr =3D address & TARGET_PAGE_MASK; > =A0 =A0 =A0 =A0 prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; > =A0 =A0 =A0 =A0 tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAG= E_SIZE); > =A0 =A0 =A0 =A0 return 0; > @@ -704,17 +702,16 @@ static int get_physical_address(CPUSPARCState > *env, target_phys_addr_t *physical > =A0int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong > address, int rw, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0int mmu_id= x) > =A0{ > - =A0 =A0target_ulong virt_addr, vaddr; > + =A0 =A0target_ulong vaddr; > =A0 =A0 target_phys_addr_t paddr; > =A0 =A0 target_ulong page_size; > =A0 =A0 int error_code =3D 0, prot, access_index; > > + =A0 =A0address &=3D TARGET_PAGE_MASK; > =A0 =A0 error_code =3D get_physical_address(env, &paddr, &prot, &access_i= ndex, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 address, rw, mmu_idx, &page_size); > =A0 =A0 if (error_code =3D=3D 0) { > - =A0 =A0 =A0 =A0virt_addr =3D address & TARGET_PAGE_MASK; > - =A0 =A0 =A0 =A0vaddr =3D virt_addr + ((address & TARGET_PAGE_MASK) & > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (TARGET_PAGE_SI= ZE - 1)); > + =A0 =A0 =A0 =A0vaddr =3D address; > > =A0 =A0 =A0 =A0 trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->= tl, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0en= v->dmmu.mmu_primary_context, > -- > 1.7.9 > --=20 Regards, Artyom Tarasenko solaris/sparc under qemu blog: http://tyom.blogspot.com/search/label/qemu