From: Artyom Tarasenko <atar4qemu@gmail.com>
To: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Blue Swirl <blauwirbel@gmail.com>, qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 2/2] apb: implement PCI bus error interrupt map registers
Date: Thu, 28 Aug 2014 13:15:43 +0200 [thread overview]
Message-ID: <CACXAS8DXHz5eri-g4TGnxy54wREYg2uijW_Mpj4xV_RitTTtCw@mail.gmail.com> (raw)
In-Reply-To: <1408989500-5652-3-git-send-email-mark.cave-ayland@ilande.co.uk>
On Mon, Aug 25, 2014 at 7:58 PM, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
> Both OpenBSD and FreeBSD SPARC64 attempt to read the interrupt map from the
> hardware and will fail if the correct ino isn't present.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
> hw/pci-host/apb.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index 3b7fb13..d2c5c14 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -147,6 +147,7 @@ typedef struct APBState {
> IOMMUState iommu;
> uint32_t pci_control[16];
> uint32_t pci_irq_map[8];
> + uint32_t pci_err_irq_map[4];
> uint32_t obio_irq_map[32];
> qemu_irq *pbm_irqs;
> qemu_irq *ivec_irqs;
> @@ -441,7 +442,7 @@ static void apb_config_writel (void *opaque, hwaddr addr,
> pbm_check_irqs(s);
> }
> break;
> - case 0x1000 ... 0x1080: /* OBIO interrupt control */
> + case 0x1000 ... 0x107f: /* OBIO interrupt control */
> if (addr & 4) {
> unsigned int ino = ((addr & 0xff) >> 3);
> s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
> @@ -519,13 +520,20 @@ static uint64_t apb_config_readl (void *opaque,
> val = 0;
> }
> break;
> - case 0x1000 ... 0x1080: /* OBIO interrupt control */
> + case 0x1000 ... 0x107f: /* OBIO interrupt control */
> if (addr & 4) {
> val = s->obio_irq_map[(addr & 0xff) >> 3];
> } else {
> val = 0;
> }
> break;
> + case 0x1080 ... 0x108f: /* PCI bus error */
> + if (addr & 4) {
> + val = s->pci_err_irq_map[(addr & 0xf) >> 3];
> + } else {
> + val = 0;
> + }
> + break;
> case 0x2000 ... 0x202f: /* PCI control */
> val = s->pci_control[(addr & 0x3f) >> 2];
> break;
> @@ -763,6 +771,9 @@ static int pci_pbm_init_device(SysBusDevice *dev)
> for (i = 0; i < 8; i++) {
> s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
> }
> + for (i = 0; i < 2; i++) {
> + s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
> + }
> for (i = 0; i < 32; i++) {
> s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
> }
> --
> 1.7.10.4
>
>
--
Regards,
Artyom Tarasenko
linux/sparc and solaris/sparc under qemu blog:
http://tyom.blogspot.com/search/label/qemu
prev parent reply other threads:[~2014-08-28 11:16 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-25 17:58 [Qemu-devel] [PATCH 0/2] apb: more PCI fixes Mark Cave-Ayland
2014-08-25 17:58 ` [Qemu-devel] [PATCH 1/2] apb: add implementation of UltraSPARC IIi PCI TAS register Mark Cave-Ayland
2014-08-28 11:33 ` Artyom Tarasenko
2014-09-05 13:42 ` Mark Cave-Ayland
2014-08-25 17:58 ` [Qemu-devel] [PATCH 2/2] apb: implement PCI bus error interrupt map registers Mark Cave-Ayland
2014-08-28 11:15 ` Artyom Tarasenko [this message]
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