From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41241) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTChp-0001as-C3 for qemu-devel@nongnu.org; Tue, 09 Feb 2016 13:08:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aTCho-0007Qz-FQ for qemu-devel@nongnu.org; Tue, 09 Feb 2016 13:08:05 -0500 Received: from mail-lb0-x234.google.com ([2a00:1450:4010:c04::234]:35317) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTCho-0007Qa-21 for qemu-devel@nongnu.org; Tue, 09 Feb 2016 13:08:04 -0500 Received: by mail-lb0-x234.google.com with SMTP id bc4so104880637lbc.2 for ; Tue, 09 Feb 2016 10:08:03 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: Date: Tue, 9 Feb 2016 23:38:02 +0530 Message-ID: From: Deepak kumar Raju Content-Type: multipart/alternative; boundary=001a11c3277ecd889c052b5a321a Subject: Re: [Qemu-devel] Regarding Cortex-A7 CPU definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers --001a11c3277ecd889c052b5a321a Content-Type: text/plain; charset=UTF-8 Thanks Peter, will follow your suggestions to add CPU definitions for Cortex-A7. I need to enable GIC & Generic timer in QEMU for Cortex-A7. Can you please let me know how to go about enabling GIC & Generic timer in QEMU. Thanks in advance, Best Regards, -Deepak On Tue, Feb 9, 2016 at 3:01 PM, Peter Maydell wrote: > On 9 February 2016 at 07:43, Deepak kumar Raju > wrote: > > Can you please help me with the cortex-a7 CPU definitions/configuration > that > > I need to add in QEMU. Thanks, > > I'm afraid I don't have time to do this myself. I suggested > below how you can go about doing this yourself if you need it: > > >> You need to look at the Technical Reference Manual for the two CPUs > >> to determine the difference. As far as QEMU is concerned the things > >> to look at are: > >> * ID register values > >> * supported CPU features > >> * any implementation-specific coprocessor registers > >> > >> ...in other words, all the things we set in the > >> cortex_a15_initfn(). > > thanks > -- PMM > --001a11c3277ecd889c052b5a321a Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Thanks Peter, will follow your suggestions to add CPU= definitions for Cortex-A7.

I need to enable GIC &= amp; Generic timer in QEMU for Cortex-A7. Can you please let me know how to= go about enabling GIC & Generic timer in QEMU.

Thanks in advance,

Best Regards,
-Deep= ak

On = Tue, Feb 9, 2016 at 3:01 PM, Peter Maydell <peter.maydell@linaro.or= g> wrote:
On 9 February 201= 6 at 07:43, Deepak kumar Raju
<raju.deepakkumar@gm= ail.com> wrote:
> Can you please help me with the cortex-a7 CPU definitions/configuratio= n that
> I need to add in QEMU. Thanks,

I'm afraid I don't have time to do this myself. I suggested<= br> below how you can go about doing this yourself if you need it:

>> You need to look at the Technical Reference Manual for the two CPU= s
>> to determine the difference. As far as QEMU is concerned the thing= s
>> to look at are:
>>=C2=A0 * ID register values
>>=C2=A0 * supported CPU features
>>=C2=A0 * any implementation-specific coprocessor registers
>>
>> ...in other words, all the things we set in the
>> cortex_a15_initfn().

thanks
-- PMM

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