[Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

[Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

[Dayeol Lee]

pmp_read_cfg() returns 8-bit value, which is combined together to form a single pmpcfg CSR. 
The default promotion rules will result in an integer here ("i*8" is integer, which
flows through) resulting in a 32-bit signed value on most hosts.
That's bogus on RV64I, with the high bits of the CSR being wrong.

Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/pmp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index c828950..3d3906a 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -330,7 +330,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
 {
     int i;
     target_ulong cfg_val = 0;
-    uint8_t val = 0;
+    target_ulong val = 0;
 
     if(sizeof(target_ulong) == 8)
         reg_index /= 2;
-- 
2.7.4

Re: [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

[Dayeol Lee]

Hi,

I submitted the patch, but just found this has been already fixed by
Michael Clark
and pushed to riscv/riscv-qemu https://github.com/riscv/riscv-qemu/pull/166
but not in the upstream.

Do we still need this patch?

Thanks,

Dayeol

On Fri, Oct 26, 2018 at 11:04 AM Dayeol Lee <dayeol@berkeley.edu> wrote:

> pmp_read_cfg() returns 8-bit value, which is combined together to form a
> single pmpcfg CSR.
> The default promotion rules will result in an integer here ("i*8" is
> integer, which
> flows through) resulting in a 32-bit signed value on most hosts.
> That's bogus on RV64I, with the high bits of the CSR being wrong.
>
> Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> ---
>  target/riscv/pmp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index c828950..3d3906a 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -330,7 +330,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env,
> uint32_t reg_index)
>  {
>      int i;
>      target_ulong cfg_val = 0;
> -    uint8_t val = 0;
> +    target_ulong val = 0;
>
>      if(sizeof(target_ulong) == 8)
>          reg_index /= 2;
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

[Alistair Francis]

On Fri, Oct 26, 2018 at 7:14 PM Dayeol Lee <dayeol@berkeley.edu> wrote:
>
> Hi,
>
> I submitted the patch, but just found this has been already fixed by
> Michael Clark
> and pushed to riscv/riscv-qemu https://github.com/riscv/riscv-qemu/pull/166
> but not in the upstream.
>
> Do we still need this patch?

Yeah, this patch is still needed as it fixes the problem in mainline.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> Thanks,
>
> Dayeol
>
> On Fri, Oct 26, 2018 at 11:04 AM Dayeol Lee <dayeol@berkeley.edu> wrote:
>
> > pmp_read_cfg() returns 8-bit value, which is combined together to form a
> > single pmpcfg CSR.
> > The default promotion rules will result in an integer here ("i*8" is
> > integer, which
> > flows through) resulting in a 32-bit signed value on most hosts.
> > That's bogus on RV64I, with the high bits of the CSR being wrong.
> >
> > Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
> > Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> > ---
> >  target/riscv/pmp.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> > index c828950..3d3906a 100644
> > --- a/target/riscv/pmp.c
> > +++ b/target/riscv/pmp.c
> > @@ -330,7 +330,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env,
> > uint32_t reg_index)
> >  {
> >      int i;
> >      target_ulong cfg_val = 0;
> > -    uint8_t val = 0;
> > +    target_ulong val = 0;
> >
> >      if(sizeof(target_ulong) == 8)
> >          reg_index /= 2;
> > --
> > 2.7.4
> >
> >

Re: [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

[Palmer Dabbelt]

On Sat, 27 Oct 2018 01:42:02 PDT (-0700), alistair23@gmail.com wrote:
> On Fri, Oct 26, 2018 at 7:14 PM Dayeol Lee <dayeol@berkeley.edu> wrote:
>>
>> Hi,
>>
>> I submitted the patch, but just found this has been already fixed by
>> Michael Clark
>> and pushed to riscv/riscv-qemu https://github.com/riscv/riscv-qemu/pull/166
>> but not in the upstream.
>>
>> Do we still need this patch?
>
> Yeah, this patch is still needed as it fixes the problem in mainline.
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> Alistair

Thanks.  I added this to for-master, I'll include it with this week's PR.

>
>>
>> Thanks,
>>
>> Dayeol
>>
>> On Fri, Oct 26, 2018 at 11:04 AM Dayeol Lee <dayeol@berkeley.edu> wrote:
>>
>> > pmp_read_cfg() returns 8-bit value, which is combined together to form a
>> > single pmpcfg CSR.
>> > The default promotion rules will result in an integer here ("i*8" is
>> > integer, which
>> > flows through) resulting in a 32-bit signed value on most hosts.
>> > That's bogus on RV64I, with the high bits of the CSR being wrong.
>> >
>> > Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
>> > Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>> > ---
>> >  target/riscv/pmp.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
>> > index c828950..3d3906a 100644
>> > --- a/target/riscv/pmp.c
>> > +++ b/target/riscv/pmp.c
>> > @@ -330,7 +330,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env,
>> > uint32_t reg_index)
>> >  {
>> >      int i;
>> >      target_ulong cfg_val = 0;
>> > -    uint8_t val = 0;
>> > +    target_ulong val = 0;
>> >
>> >      if(sizeof(target_ulong) == 8)
>> >          reg_index /= 2;
>> > --
>> > 2.7.4
>> >
>> >