From: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org, "Cameron Esfahani" <dirty@apple.com>,
"Julian Armistead" <julian.armistead@linaro.org>,
"Radoslaw Biernacki" <rad@semihalf.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Phil Dennis-Jordan" <phil@philjordan.eu>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-arm@nongnu.org, "Roman Bolshakov" <rbolshakov@ddn.com>,
"Alexander Graf" <agraf@csgraf.de>
Subject: Re: [PATCH 19/20] hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition
Date: Thu, 19 Jun 2025 14:36:43 +0100 [thread overview]
Message-ID: <CAD=n3R2GC0vFxkpzwiieVGSptPYdAEz++d34Z5Qwmn=mKDdwGg@mail.gmail.com> (raw)
In-Reply-To: <20250619131319.47301-20-philmd@linaro.org>
On Thu, 19 Jun 2025 at 14:15, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> Define RAMLIMIT_BYTES using the TiB definition and display
> the error parsed with size_to_str():
>
> $ qemu-system-aarch64-unsigned -M sbsa-ref -m 9T
> qemu-system-aarch64-unsigned: sbsa-ref: cannot model more than 8 TiB of RAM
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
/
Leif
> ---
> hw/arm/sbsa-ref.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index deae5cf9861..3b7d4e7bf1d 100644
> --- a/hw/arm/sbsa-ref.c
> +++ b/hw/arm/sbsa-ref.c
> @@ -19,6 +19,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/cutils.h"
> #include "qemu/datadir.h"
> #include "qapi/error.h"
> #include "qemu/error-report.h"
> @@ -53,8 +54,7 @@
> #include "target/arm/cpu-qom.h"
> #include "target/arm/gtimer.h"
>
> -#define RAMLIMIT_GB 8192
> -#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
> +#define RAMLIMIT_BYTES (8 * TiB)
>
> #define NUM_IRQS 256
> #define NUM_SMMU_IRQS 4
> @@ -756,7 +756,9 @@ static void sbsa_ref_init(MachineState *machine)
> sms->smp_cpus = smp_cpus;
>
> if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
> - error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
> + g_autofree char *size_str = size_to_str(RAMLIMIT_BYTES);
> +
> + error_report("sbsa-ref: cannot model more than %s of RAM", size_str);
> exit(1);
> }
>
> --
> 2.49.0
>
next prev parent reply other threads:[~2025-06-19 13:38 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-19 13:12 [PATCH 00/20] arm: Fixes and preparatory cleanups for split-accel Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 01/20] target/arm: Remove arm_handle_psci_call() stub Philippe Mathieu-Daudé
2025-06-19 21:10 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 02/20] target/arm: Reduce arm_cpu_post_init() declaration scope Philippe Mathieu-Daudé
2025-06-19 21:10 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 03/20] target/arm: Unify gen_exception_internal() Philippe Mathieu-Daudé
2025-06-19 21:12 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 04/20] target/arm/hvf: Simplify GIC hvf_arch_init_vcpu() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 05/20] target/arm/hvf: Directly re-lock BQL after hv_vcpu_run() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 06/20] target/arm/hvf: Trace hv_vcpu_run() failures Philippe Mathieu-Daudé
2025-06-19 21:14 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 07/20] accel/hvf: Trace VM memory mapping Philippe Mathieu-Daudé
2025-06-19 22:41 ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 08/20] target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event Philippe Mathieu-Daudé
2025-06-19 21:17 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 09/20] target/arm/hvf: Correct dtb_compatible value Philippe Mathieu-Daudé
2025-06-19 21:18 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 10/20] target/arm: Restrict system register properties to system binary Philippe Mathieu-Daudé
2025-06-19 21:18 ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 11/20] target/arm: Create GTimers *after* features finalized / accel realized Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 12/20] accel: Keep reference to AccelOpsClass in AccelClass Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 13/20] accel: Introduce AccelOpsClass::cpu_target_realize() hook Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 14/20] accel/hvf: Add hvf_arch_cpu_realize() stubs Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 15/20] target/arm/hvf: Really set Generic Timer counter frequency Philippe Mathieu-Daudé
2025-06-19 21:21 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 16/20] hw/arm/virt: Only require TCG || QTest to use TrustZone Philippe Mathieu-Daudé
2025-06-19 21:22 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 17/20] hw/arm/virt: Only require TCG || QTest to use virtualization extension Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 18/20] hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 19/20] hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition Philippe Mathieu-Daudé
2025-06-19 13:36 ` Leif Lindholm [this message]
2025-06-19 21:09 ` Richard Henderson
2025-06-19 21:20 ` Philippe Mathieu-Daudé
2025-06-19 21:28 ` Richard Henderson
2025-06-19 21:34 ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 20/20] tests/functional/sbsa-ref: Move where machine type is set Philippe Mathieu-Daudé
2025-06-19 13:23 ` Philippe Mathieu-Daudé
2025-06-19 14:40 ` Leif Lindholm
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