From: Stevie Lavern <stevie.lavern@gmail.com>
To: qemu-devel@nongnu.org
Cc: eduardo@habkost.net, Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
stevie.lavern@gmail.com
Subject: [PATCH] i386/tcg: generate an illegal op when translating AVX instructions
Date: Thu, 6 Jan 2022 11:35:42 +0100 [thread overview]
Message-ID: <CADV2EAuttJSjXMc1CHmyJ9ApjOFLJ8CKxa81LLQp3DAYn2A2ZA@mail.gmail.com> (raw)
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The AVX instruction set is not supported by Qemu.
However, some AVX instructions are properly decoded and emulated as their
legacy SSE version.
This patch prevent this by generating an illegal_op instead of a bogus SSE
instruction.
Signed-off-by: Stevie Lavern <stevie.lavern@gmail.com>
---
target/i386/tcg/translate.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 05f9336c9b..996fce65b2 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4706,6 +4706,11 @@ static target_ulong disas_insn(DisasContext *s,
CPUState *cpu)
}
}
+ if (s->vex_l & 1) {
+ /* If set, registers are 256bits.
+ Fail as AVX extension is not supported. */
+ goto illegal_op;
+ }
s->prefix = prefixes;
s->aflag = aflag;
s->dflag = dflag;
--
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next reply other threads:[~2022-01-06 10:38 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-06 10:35 Stevie Lavern [this message]
2022-01-06 18:22 ` [PATCH] i386/tcg: generate an illegal op when translating AVX instructions Richard Henderson
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