From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6CDAC6FD1F for ; Tue, 19 Mar 2024 16:24:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rmcGA-0004GB-70; Tue, 19 Mar 2024 12:24:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rmcG0-00044u-Jp for qemu-devel@nongnu.org; Tue, 19 Mar 2024 12:24:09 -0400 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rmcFy-0005Cr-E3 for qemu-devel@nongnu.org; Tue, 19 Mar 2024 12:24:08 -0400 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2d46dd5f222so65126311fa.1 for ; Tue, 19 Mar 2024 09:24:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1710865443; x=1711470243; darn=nongnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=H97QZ2h29BVhDMviywLLHMLCg3ZLWp6ny3RK33EvOZ0=; b=Pyo2b1FjmdWVzePkjwCOsVKzkawecq3mXm8ZtuuR2Dv5qVtPMVDiCnrqcD11CVK94P R0udZMo89wTOzZcHEgaXyfTpR9riDvv0kMZeRxWrFTttWLyuhPZujNgXucKQSDEshcvl u4U99JMbpLRwE7oqP8U8dAHwaY3/TMfXF1avqT5eH+Ye4lAG3vRCyrgxC1lxXlsROken nrItAi0mY31uf9SLKeBLP1mfMOqymXgYI+QWkkOuhFpUTgbcDSnNx2dP467QB3gD/Txb +GiheAEpb5K6bdKULtQC0wFDTTyLZF85dau9ffpx24U+cdd7xglwNCA/CK0Xkq2HW8yj T1tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710865443; x=1711470243; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=H97QZ2h29BVhDMviywLLHMLCg3ZLWp6ny3RK33EvOZ0=; b=cohKCi0jrbE3YDCtmEtt83eZ4MODOiaRglwK1hCJ7SbCv9VLfrUP3ZyIvHAo7qNl+F EuQR91EiTAeFkJOF5o8+DkkaV95F9qmdvKpoyWVk9E4Q9o2gIEvb63OAJ6G58848cjZK YKTxNFNC9POqit41S55ddsDXd4xgkmtatOxOE2aP17V/lwvfim0ZcLOmADB1eEgTDmPQ X9rcVKloUMDS6sA6g7FszurMQhB/rQIf1WcVwe6Jk944/rcNfZu5eJ3yS9AxVobH698k I1rx84z9RMFlVBFQ3dHPARt68UAaDAi1ePklUiVqfHzl6tGFNKfPngEPMQwQptMMGhc5 tKfg== X-Gm-Message-State: AOJu0Yy9rHFr6ijf43CtTh8Fx+2x4rUcKn6GXH/G39bN7pxvcA/zAxFK AxKlxuPH07L0AWZFJpYvBOoyh2jMI6oBie7GHlCvnsh9OjCrng7d0BywBF2u+G38IK4uGm/Kouy Va6FczbUwwhIha1LIX57TXlrQ9uz4C4Nq77+uoJFnmRYGLXysvjk= X-Google-Smtp-Source: AGHT+IGanRU9nHcR1jelNUTw1BVINs028Ev1R6cGg60nAg8esRtaJCfzkpzQ2gfQxUFbH+GcQ7JLP7yctUe4+T5z3eM= X-Received: by 2002:a2e:8552:0:b0:2d4:22d9:b015 with SMTP id u18-20020a2e8552000000b002d422d9b015mr10374325ljj.10.1710865443292; Tue, 19 Mar 2024 09:24:03 -0700 (PDT) MIME-Version: 1.0 References: <20240306170855.24341-1-jason.chien@sifive.com> <20240306170855.24341-2-jason.chien@sifive.com> In-Reply-To: <20240306170855.24341-2-jason.chien@sifive.com> From: Jason Chien Date: Wed, 20 Mar 2024 00:23:52 +0800 Message-ID: Subject: Re: [PATCH 1/5] target/riscv: Add support for Zve32x extension To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang , Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Richard Henderson , Andrew Jones Content-Type: multipart/alternative; boundary="00000000000001a1bf061405e776" Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=jason.chien@sifive.com; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --00000000000001a1bf061405e776 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Ping. Can anyone review the patches please? Jason Chien =E6=96=BC 2024=E5=B9=B43=E6=9C=887=E6= =97=A5 =E9=80=B1=E5=9B=9B =E4=B8=8A=E5=8D=881:09=E5=AF=AB=E9=81=93=EF=BC=9A > Add support for Zve32x extension and replace some checks for Zve32f with > Zve32x, since Zve32f depends on Zve32x. > > Signed-off-by: Jason Chien > Reviewed-by: Frank Chang > Reviewed-by: Max Chou > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu_cfg.h | 1 + > target/riscv/cpu_helper.c | 2 +- > target/riscv/csr.c | 2 +- > target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- > target/riscv/tcg/tcg-cpu.c | 16 ++++++++-------- > 6 files changed, 14 insertions(+), 12 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index fd0c7efdda..10ccae3323 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -152,6 +152,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { > ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), > ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), > ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), > + ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x), > ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), > ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), > ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index be39870691..beb3d10213 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -90,6 +90,7 @@ struct RISCVCPUConfig { > bool ext_zhinx; > bool ext_zhinxmin; > bool ext_zve32f; > + bool ext_zve32x; > bool ext_zve64f; > bool ext_zve64d; > bool ext_zvbb; > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index c994a72634..ebbe56d9a2 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -72,7 +72,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc= , > *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; > *cs_base =3D 0; > > - if (cpu->cfg.ext_zve32f) { > + if (cpu->cfg.ext_zve32x) { > /* > * If env->vl equals to VLMAX, we can use generic vector operati= on > * expanders (GVEC) to accerlate the vector operations. > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 726096444f..d96feea5d3 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -93,7 +93,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) > > static RISCVException vs(CPURISCVState *env, int csrno) > { > - if (riscv_cpu_cfg(env)->ext_zve32f) { > + if (riscv_cpu_cfg(env)->ext_zve32x) { > #if !defined(CONFIG_USER_ONLY) > if (!env->debugger && !riscv_cpu_vector_enabled(env)) { > return RISCV_EXCP_ILLEGAL_INST; > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc > b/target/riscv/insn_trans/trans_rvv.c.inc > index 9e101ab434..f00f1ee886 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -149,7 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int > rs1, TCGv s2) > { > TCGv s1, dst; > > - if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) { > + if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) { > return false; > } > > @@ -179,7 +179,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv > s1, TCGv s2) > { > TCGv dst; > > - if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) { > + if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) { > return false; > } > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index ab6db817db..ce539528e6 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -501,9 +501,13 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu= , > Error **errp) > return; > } > > - if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { > - error_setg(errp, "Zve32f/Zve64f extensions require F extension")= ; > - return; > + /* The Zve32f extension depends on the Zve32x extension */ > + if (cpu->cfg.ext_zve32f) { > + if (!riscv_has_ext(env, RVF)) { > + error_setg(errp, "Zve32f/Zve64f extensions require F > extension"); > + return; > + } > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true); > } > > if (cpu->cfg.ext_zvfh) { > @@ -653,13 +657,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu= , > Error **errp) > cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); > } > > - /* > - * In principle Zve*x would also suffice here, were they supported > - * in qemu > - */ > if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || > cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || > cpu->cfg.ext_zvksed || > - cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { > + cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { > error_setg(errp, > "Vector crypto extensions require V or Zve* > extensions"); > return; > -- > 2.43.2 > > --00000000000001a1bf061405e776 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Ping. Can anyone review the patches please?

<= div class=3D"gmail_quote">
Jason Chien= <jason.chien@sifive.com&g= t; =E6=96=BC 2024=E5=B9=B43=E6=9C=887=E6=97=A5 =E9=80=B1=E5=9B=9B =E4=B8=8A= =E5=8D=881:09=E5=AF=AB=E9=81=93=EF=BC=9A
Add support for Zve32x extension and replace some = checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
=C2=A0target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 1 +
=C2=A0target/riscv/cpu_cfg.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 1 +
=C2=A0target/riscv/cpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 2 +-
=C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 +-
=C2=A0target/riscv/insn_trans/trans_rvv.c.inc |=C2=A0 4 ++--
=C2=A0target/riscv/tcg/tcg-cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 | 16 ++++++++--------
=C2=A06 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fd0c7efdda..10ccae3323 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -152,6 +152,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D {
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb)= ,
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc)= ,
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve= 32f),
+=C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),=
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve= 64f),
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve= 64d),
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_z= vfbfmin),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index be39870691..beb3d10213 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -90,6 +90,7 @@ struct RISCVCPUConfig {
=C2=A0 =C2=A0 =C2=A0bool ext_zhinx;
=C2=A0 =C2=A0 =C2=A0bool ext_zhinxmin;
=C2=A0 =C2=A0 =C2=A0bool ext_zve32f;
+=C2=A0 =C2=A0 bool ext_zve32x;
=C2=A0 =C2=A0 =C2=A0bool ext_zve64f;
=C2=A0 =C2=A0 =C2=A0bool ext_zve64d;
=C2=A0 =C2=A0 =C2=A0bool ext_zvbb;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c994a72634..ebbe56d9a2 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -72,7 +72,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,<= br> =C2=A0 =C2=A0 =C2=A0*pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & U= INT32_MAX : env->pc;
=C2=A0 =C2=A0 =C2=A0*cs_base =3D 0;

-=C2=A0 =C2=A0 if (cpu->cfg.ext_zve32f) {
+=C2=A0 =C2=A0 if (cpu->cfg.ext_zve32x) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 * If env->vl equals to VLMAX, we can = use generic vector operation
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 * expanders (GVEC) to accerlate the vect= or operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 726096444f..d96feea5d3 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -93,7 +93,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
=C2=A0static RISCVException vs(CPURISCVState *env, int csrno)
=C2=A0{
-=C2=A0 =C2=A0 if (riscv_cpu_cfg(env)->ext_zve32f) {
+=C2=A0 =C2=A0 if (riscv_cpu_cfg(env)->ext_zve32x) {
=C2=A0#if !defined(CONFIG_USER_ONLY)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (!env->debugger && !riscv_c= pu_vector_enabled(env)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return RISCV_EXCP_ILLEGAL_I= NST;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc
index 9e101ab434..f00f1ee886 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -149,7 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,= TCGv s2)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0TCGv s1, dst;

-=C2=A0 =C2=A0 if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+=C2=A0 =C2=A0 if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return false;
=C2=A0 =C2=A0 =C2=A0}

@@ -179,7 +179,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s= 1, TCGv s2)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0TCGv dst;

-=C2=A0 =C2=A0 if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+=C2=A0 =C2=A0 if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return false;
=C2=A0 =C2=A0 =C2=A0}

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index ab6db817db..ce539528e6 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -501,9 +501,13 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
=C2=A0 =C2=A0 =C2=A0}

-=C2=A0 =C2=A0 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RV= F)) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_setg(errp, "Zve32f/Zve64f extension= s require F extension");
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 /* The Zve32f extension depends on the Zve32x extension */ +=C2=A0 =C2=A0 if (cpu->cfg.ext_zve32f) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!riscv_has_ext(env, RVF)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 error_setg(errp, "Zve32f/Zv= e64f extensions require F extension");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ex= t_zve32x), true);
=C2=A0 =C2=A0 =C2=A0}

=C2=A0 =C2=A0 =C2=A0if (cpu->cfg.ext_zvfh) {
@@ -653,13 +657,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFS= ET(ext_zvbc), true);
=C2=A0 =C2=A0 =C2=A0}

-=C2=A0 =C2=A0 /*
-=C2=A0 =C2=A0 =C2=A0* In principle Zve*x would also suffice here, were the= y supported
-=C2=A0 =C2=A0 =C2=A0* in qemu
-=C2=A0 =C2=A0 =C2=A0*/
=C2=A0 =C2=A0 =C2=A0if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cp= u->cfg.ext_zvkg ||
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu->cfg.ext_zvkned || cpu->cfg.ex= t_zvknha || cpu->cfg.ext_zvksed ||
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu->cfg.ext_zvksh) && !cpu-&= gt;cfg.ext_zve32f) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu->cfg.ext_zvksh) && !cpu-&= gt;cfg.ext_zve32x) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0error_setg(errp,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "= ;Vector crypto extensions require V or Zve* extensions");
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
--
2.43.2

--00000000000001a1bf061405e776--