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To: Frank Chang Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, tech-control-transfer-records@lists.riscv.org, jason.chien@sifive.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Aug 27, 2024 at 10:28=E2=80=AFAM Frank Chang wrote: > > Rajnesh Kanwal =E6=96=BC 2024=E5=B9=B46=E6=9C=8819= =E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=8811:27=E5=AF=AB=E9=81=93=EF= =BC=9A > > > > This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and > > sctrdepth CSRs handling. > > > > Signed-off-by: Rajnesh Kanwal > > --- > > target/riscv/cpu.h | 5 ++ > > target/riscv/cpu_cfg.h | 2 + > > target/riscv/csr.c | 128 +++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 135 insertions(+) > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index a185e2d494..3d4d5172b8 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -263,6 +263,11 @@ struct CPUArchState { > > target_ulong mcause; > > target_ulong mtval; /* since: priv-1.10.0 */ > > > > + uint64_t mctrctl; > > + uint32_t sctrdepth; > > + uint32_t sctrstatus; > > + uint64_t vsctrctl; > > + > > /* Machine and Supervisor interrupt priorities */ > > uint8_t miprio[64]; > > uint8_t siprio[64]; > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > > index d9354dc80a..d329a65811 100644 > > --- a/target/riscv/cpu_cfg.h > > +++ b/target/riscv/cpu_cfg.h > > @@ -123,6 +123,8 @@ struct RISCVCPUConfig { > > bool ext_zvfhmin; > > bool ext_smaia; > > bool ext_ssaia; > > + bool ext_smctr; > > + bool ext_ssctr; > > Base on: https://github.com/riscv/riscv-control-transfer-records/pull/29 > Smctr and Ssctr depend on both S-mode and Sscsrind. > We should add the implied rules for Smctr and Ssctr. > > Regards, > Frank Chang Hi Frank, Are you referring to the checks in riscv_cpu_validate_set_extensions()? These checks are already present in the last patch. https://lore.kernel.org/qemu-riscv/20240619152708.135991-7-rkanwal@rivosinc= .com/ > > > > bool ext_sscofpmf; > > bool ext_smepmp; > > bool rvv_ta_all_1s; > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 2f92e4b717..0b5bf4d050 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -621,6 +621,48 @@ static RISCVException pointer_masking(CPURISCVStat= e *env, int csrno) > > return RISCV_EXCP_ILLEGAL_INST; > > } > > > > +/* > > + * M-mode: > > + * Without ext_smctr raise illegal inst excep. > > + * Otherwise everything is accessible to m-mode. > > + * > > + * S-mode: > > + * Without ext_ssctr or mstateen.ctr raise illegal inst excep. > > + * Otherwise everything other than mctrctl is accessible. > > + * > > + * VS-mode: > > + * Without ext_ssctr or mstateen.ctr raise illegal inst excep. > > + * Without hstateen.ctr raise virtual illegal inst excep. > > + * Otherwise allow sctrctl (vsctrctl), sctrstatus, 0x200-0x2ff entry r= ange. > > + * Always raise illegal instruction exception for sctrdepth. > > + */ > > +static RISCVException ctr_mmode(CPURISCVState *env, int csrno) > > +{ > > + /* Check if smctr-ext is present */ > > + if (riscv_cpu_cfg(env)->ext_smctr) { > > + return RISCV_EXCP_NONE; > > + } > > + > > + return RISCV_EXCP_ILLEGAL_INST; > > +} > > + > > +static RISCVException ctr_smode(CPURISCVState *env, int csrno) > > +{ > > + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); > > + > > + if (!cfg->ext_smctr && !cfg->ext_ssctr) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_CTR); > > + if (ret =3D=3D RISCV_EXCP_NONE && csrno =3D=3D CSR_SCTRDEPTH && > > + env->virt_enabled) { > > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > > + } > > + > > + return ret; > > +} > > + > > static RISCVException aia_hmode(CPURISCVState *env, int csrno) > > { > > int ret; > > @@ -3835,6 +3877,86 @@ static RISCVException write_satp(CPURISCVState *= env, int csrno, > > return RISCV_EXCP_NONE; > > } > > > > +static RISCVException rmw_sctrdepth(CPURISCVState *env, int csrno, > > + target_ulong *ret_val, > > + target_ulong new_val, target_ulong= wr_mask) > > +{ > > + uint64_t mask =3D wr_mask & SCTRDEPTH_MASK; > > + > > + if (ret_val) { > > + *ret_val =3D env->sctrdepth; > > + } > > + > > + env->sctrdepth =3D (env->sctrdepth & ~mask) | (new_val & mask); > > + > > + /* Correct depth. */ > > + if (wr_mask & SCTRDEPTH_MASK) { > > + uint64_t depth =3D get_field(env->sctrdepth, SCTRDEPTH_MASK); > > + > > + if (depth > SCTRDEPTH_MAX) { > > + depth =3D SCTRDEPTH_MAX; > > + env->sctrdepth =3D set_field(env->sctrdepth, SCTRDEPTH_MAS= K, depth); > > + } > > + > > + /* Update sctrstatus.WRPTR with a legal value */ > > + depth =3D 16 << depth; > > + env->sctrstatus =3D > > + env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1)); > > + } > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException rmw_sctrstatus(CPURISCVState *env, int csrno, > > + target_ulong *ret_val, > > + target_ulong new_val, target_ulon= g wr_mask) > > +{ > > + uint32_t depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK)= ; > > + uint32_t mask =3D wr_mask & SCTRSTATUS_MASK; > > + > > + if (ret_val) { > > + *ret_val =3D env->sctrstatus; > > + } > > + > > + env->sctrstatus =3D (env->sctrstatus & ~mask) | (new_val & mask); > > + > > + /* Update sctrstatus.WRPTR with a legal value */ > > + env->sctrstatus =3D env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (d= epth - 1)); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException rmw_xctrctl(CPURISCVState *env, int csrno, > > + target_ulong *ret_val, > > + target_ulong new_val, target_ulong= wr_mask) > > +{ > > + uint64_t csr_mask, mask =3D wr_mask; > > + uint64_t *ctl_ptr =3D &env->mctrctl; > > + > > + if (csrno =3D=3D CSR_MCTRCTL) { > > + csr_mask =3D MCTRCTL_MASK; > > + } else if (csrno =3D=3D CSR_SCTRCTL && !env->virt_enabled) { > > + csr_mask =3D SCTRCTL_MASK; > > + } else { > > + /* > > + * This is for csrno =3D=3D CSR_SCTRCTL and env->virt_enabled = =3D=3D true > > + * or csrno =3D=3D CSR_VSCTRCTL. > > + */ > > + csr_mask =3D VSCTRCTL_MASK; > > + ctl_ptr =3D &env->vsctrctl; > > + } > > + > > + mask &=3D csr_mask; > > + > > + if (ret_val) { > > + *ret_val =3D *ctl_ptr & csr_mask; > > + } > > + > > + *ctl_ptr =3D (*ctl_ptr & ~mask) | (new_val & mask); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > static RISCVException read_vstopi(CPURISCVState *env, int csrno, > > target_ulong *val) > > { > > @@ -5771,6 +5893,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D= { > > [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, > > write_spmbase = }, > > > > + [CSR_MCTRCTL] =3D { "mctrctl", ctr_mmode, NULL, NULL, rmw_x= ctrctl }, > > + [CSR_SCTRCTL] =3D { "sctrctl", ctr_smode, NULL, NULL, rmw_x= ctrctl }, > > + [CSR_VSCTRCTL] =3D { "vsctrctl", ctr_smode, NULL, NULL, rmw_x= ctrctl }, > > + [CSR_SCTRDEPTH] =3D { "sctrdepth", ctr_smode, NULL, NULL, rmw_s= ctrdepth }, > > + [CSR_SCTRSTATUS] =3D { "sctrstatus", ctr_smode, NULL, NULL, rmw_s= ctrstatus }, > > + > > /* Performance Counters */ > > [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcount= er }, > > [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_hpmcount= er }, > > -- > > 2.34.1 > > > >