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To: Alistair Francis Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, jason.chien@sifive.com, frank.chang@sifive.com, richard.henderson@linaro.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Feb 3, 2025 at 2:58=E2=80=AFAM Alistair Francis wrote: > > On Thu, Dec 5, 2024 at 9:36=E2=80=AFPM Rajnesh Kanwal wrote: > > > > CTR entries are accessed using ctrsource, ctrtarget and ctrdata > > registers using smcsrind/sscsrind extension. This commits extends > > the csrind extension to support CTR registers. > > > > ctrsource is accessible through xireg CSR, ctrtarget is accessible > > through xireg1 and ctrdata is accessible through xireg2 CSR. > > > > CTR supports maximum depth of 256 entries which are accessed using > > xiselect range 0x200 to 0x2ff. > > > > This commits also adds properties to enable CTR extension. CTR can be > > enabled using smctr=3Dtrue and ssctr=3Dtrue now. > > > > Signed-off-by: Rajnesh Kanwal > > --- > > target/riscv/cpu.c | 26 +++++++- > > target/riscv/csr.c | 150 +++++++++++++++++++++++++++++++++++++= +++++++- > > target/riscv/tcg/tcg-cpu.c | 11 ++++ > > 3 files changed, 185 insertions(+), 2 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 2a4f285a974ffc62e7f3e938691dbffe376a7e46..751029e924d4690aaa5de65= 456fd5a5ec25b916a 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -199,6 +199,8 @@ const RISCVIsaExtData isa_edata_arr[] =3D { > > ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), > > ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), > > ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), > > + ISA_EXT_DATA_ENTRY(smctr, PRIV_VERSION_1_12_0, ext_smctr), > > + ISA_EXT_DATA_ENTRY(ssctr, PRIV_VERSION_1_12_0, ext_ssctr), > > ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), > > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > > @@ -1481,6 +1483,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions= [] =3D { > > MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false), > > MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false), > > MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false), > > + MULTI_EXT_CFG_BOOL("smctr", ext_smctr, false), > > + MULTI_EXT_CFG_BOOL("ssctr", ext_ssctr, false), > > This should be the very last patch (once everything is supported) > > Otherwise > > Acked-by: Alistair Francis > > Alistair I am sending v6 as I will have to rebase this series on the latest riscv-to-apply.for-upstream. I will fix the order of patches in that. Thanks Rajnesh > > > MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), > > MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false), > > MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false), > > @@ -2656,6 +2660,26 @@ static RISCVCPUImpliedExtsRule SSCFG_IMPLIED =3D= { > > }, > > }; > > > > +static RISCVCPUImpliedExtsRule SMCTR_IMPLIED =3D { > > + .ext =3D CPU_CFG_OFFSET(ext_smctr), > > + .implied_misa_exts =3D RVS, > > + .implied_multi_exts =3D { > > + CPU_CFG_OFFSET(ext_sscsrind), > > + > > + RISCV_IMPLIED_EXTS_RULE_END > > + }, > > +}; > > + > > +static RISCVCPUImpliedExtsRule SSCTR_IMPLIED =3D { > > + .ext =3D CPU_CFG_OFFSET(ext_ssctr), > > + .implied_misa_exts =3D RVS, > > + .implied_multi_exts =3D { > > + CPU_CFG_OFFSET(ext_sscsrind), > > + > > + RISCV_IMPLIED_EXTS_RULE_END > > + }, > > +}; > > + > > RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] =3D { > > &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, > > &RVM_IMPLIED, &RVV_IMPLIED, NULL > > @@ -2674,7 +2698,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_= rules[] =3D { > > &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, > > &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, > > &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, > > - NULL > > + &SMCTR_IMPLIED, &SSCTR_IMPLIED, NULL > > }; > > > > static Property riscv_cpu_properties[] =3D { > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index a399d55740c7259cd1c1d893687541e23ea3ce52..d7b520099563d3a680c5b75= dc987881caab95407 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -2399,6 +2399,13 @@ static bool xiselect_cd_range(target_ulong isel) > > return (ISELECT_CD_FIRST <=3D isel && isel <=3D ISELECT_CD_LAST); > > } > > > > +static bool xiselect_ctr_range(int csrno, target_ulong isel) > > +{ > > + /* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */ > > + return CTR_ENTRIES_FIRST <=3D isel && isel <=3D CTR_ENTRIES_LAST &= & > > + csrno < CSR_MIREG; > > +} > > + > > static int rmw_iprio(target_ulong xlen, > > target_ulong iselect, uint8_t *iprio, > > target_ulong *val, target_ulong new_val, > > @@ -2444,6 +2451,124 @@ static int rmw_iprio(target_ulong xlen, > > return 0; > > } > > > > +static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *v= al, > > + target_ulong new_val, target_ulong wr_mask) > > +{ > > + /* > > + * CTR arrays are treated as circular buffers and TOS always point= s to next > > + * empty slot, keeping TOS - 1 always pointing to latest entry. Gi= ven entry > > + * 0 is always the latest one, traversal is a bit different here. = See the > > + * below example. > > + * > > + * Depth =3D 16. > > + * > > + * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] = [E] [F] > > + * TOS H > > + * entry 6 5 4 3 2 1 0 F E D C B A 9 = 8 7 > > + */ > > + const uint64_t entry =3D isel - CTR_ENTRIES_FIRST; > > + const uint64_t depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH= _MASK); > > + uint64_t idx; > > + > > + /* Entry greater than depth-1 is read-only zero */ > > + if (entry >=3D depth) { > > + if (val) { > > + *val =3D 0; > > + } > > + return 0; > > + } > > + > > + idx =3D get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK); > > + idx =3D (idx - entry - 1) & (depth - 1); > > + > > + if (val) { > > + *val =3D env->ctr_src[idx]; > > + } > > + > > + env->ctr_src[idx] =3D (env->ctr_src[idx] & ~wr_mask) | (new_val & = wr_mask); > > + > > + return 0; > > +} > > + > > +static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *v= al, > > + target_ulong new_val, target_ulong wr_mask) > > +{ > > + /* > > + * CTR arrays are treated as circular buffers and TOS always point= s to next > > + * empty slot, keeping TOS - 1 always pointing to latest entry. Gi= ven entry > > + * 0 is always the latest one, traversal is a bit different here. = See the > > + * below example. > > + * > > + * Depth =3D 16. > > + * > > + * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] = [E] [F] > > + * head H > > + * entry 6 5 4 3 2 1 0 F E D C B A 9 = 8 7 > > + */ > > + const uint64_t entry =3D isel - CTR_ENTRIES_FIRST; > > + const uint64_t depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH= _MASK); > > + uint64_t idx; > > + > > + /* Entry greater than depth-1 is read-only zero */ > > + if (entry >=3D depth) { > > + if (val) { > > + *val =3D 0; > > + } > > + return 0; > > + } > > + > > + idx =3D get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK); > > + idx =3D (idx - entry - 1) & (depth - 1); > > + > > + if (val) { > > + *val =3D env->ctr_dst[idx]; > > + } > > + > > + env->ctr_dst[idx] =3D (env->ctr_dst[idx] & ~wr_mask) | (new_val & = wr_mask); > > + > > + return 0; > > +} > > + > > +static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val= , > > + target_ulong new_val, target_ulong wr_mask) > > +{ > > + /* > > + * CTR arrays are treated as circular buffers and TOS always point= s to next > > + * empty slot, keeping TOS - 1 always pointing to latest entry. Gi= ven entry > > + * 0 is always the latest one, traversal is a bit different here. = See the > > + * below example. > > + * > > + * Depth =3D 16. > > + * > > + * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] = [E] [F] > > + * head H > > + * entry 6 5 4 3 2 1 0 F E D C B A 9 = 8 7 > > + */ > > + const uint64_t entry =3D isel - CTR_ENTRIES_FIRST; > > + const uint64_t mask =3D wr_mask & CTRDATA_MASK; > > + const uint64_t depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH= _MASK); > > + uint64_t idx; > > + > > + /* Entry greater than depth-1 is read-only zero */ > > + if (entry >=3D depth) { > > + if (val) { > > + *val =3D 0; > > + } > > + return 0; > > + } > > + > > + idx =3D get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK); > > + idx =3D (idx - entry - 1) & (depth - 1); > > + > > + if (val) { > > + *val =3D env->ctr_data[idx]; > > + } > > + > > + env->ctr_data[idx] =3D (env->ctr_data[idx] & ~mask) | (new_val & m= ask); > > + > > + return 0; > > +} > > + > > static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno, > > target_ulong isel, target_ulong *val, > > target_ulong new_val, target_ulong wr_mask) > > @@ -2596,6 +2721,27 @@ done: > > return ret; > > } > > > > +static int rmw_xireg_ctr(CPURISCVState *env, int csrno, > > + target_ulong isel, target_ulong *val, > > + target_ulong new_val, target_ulong wr_mask) > > +{ > > + if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssc= tr) { > > + return -EINVAL; > > + } > > + > > + if (csrno =3D=3D CSR_SIREG || csrno =3D=3D CSR_VSIREG) { > > + return rmw_ctrsource(env, isel, val, new_val, wr_mask); > > + } else if (csrno =3D=3D CSR_SIREG2 || csrno =3D=3D CSR_VSIREG2) { > > + return rmw_ctrtarget(env, isel, val, new_val, wr_mask); > > + } else if (csrno =3D=3D CSR_SIREG3 || csrno =3D=3D CSR_VSIREG3) { > > + return rmw_ctrdata(env, isel, val, new_val, wr_mask); > > + } else if (val) { > > + *val =3D 0; > > + } > > + > > + return 0; > > +} > > + > > /* > > * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg= 6 > > * > > @@ -2607,11 +2753,13 @@ static int rmw_xireg_csrind(CPURISCVState *env,= int csrno, > > target_ulong isel, target_ulong *val, > > target_ulong new_val, target_ulong wr_ma= sk) > > { > > - int ret =3D -EINVAL; > > bool virt =3D csrno =3D=3D CSR_VSIREG ? true : false; > > + int ret =3D -EINVAL; > > > > if (xiselect_cd_range(isel)) { > > ret =3D rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask); > > + } else if (xiselect_ctr_range(csrno, isel)) { > > + ret =3D rmw_xireg_ctr(env, csrno, isel, val, new_val, wr_mask)= ; > > } else { > > /* > > * As per the specification, access to unimplented region is u= ndefined > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > > index 2b57aa4d1704b176f314dbe0b120cfcc943bf4f8..575b5692c7f68a5f6d37edb= c17269e41f496f682 100644 > > --- a/target/riscv/tcg/tcg-cpu.c > > +++ b/target/riscv/tcg/tcg-cpu.c > > @@ -652,6 +652,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *c= pu, Error **errp) > > return; > > } > > > > + if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && > > + (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { > > + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || > > + cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { > > + error_setg(errp, "Smctr and Ssctr require S-mode and Sscsr= ind"); > > + return; > > + } > > + cpu->cfg.ext_smctr =3D false; > > + cpu->cfg.ext_ssctr =3D false; > > + } > > + > > /* > > * Disable isa extensions based on priv spec after we > > * validated and set everything we need. > > > > -- > > 2.34.1 > > > >